Quasisaturation Effect and Optimization for 4H-SiC Trench MOSFET With P+ Shielding Region

Fu, Hao; Wei, Jiaxing; Wei, Zhaoxiang; Liu, Siyang; Ni, Lihua; Yang, Zenan; Sun, Weifeng

doi:10.1109/ted.2021.3096919

Cited by 7 publications

(4 citation statements)

References 26 publications

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“…Therefore, it is necessary to design a structure that suppresses the electric field at the gate oxide to ensure the safety and commercialization of SiC trench MOSFETs. [16][17][18][19][20][21][22][23][24][25][26][27][28] Bottom protection p-well (BPW) and double-trench MOSFETs are representative structures for suppressing the electric field crowded on the gate oxide. 29,30) However, BPW has considerable disadvantages depending on the thickness of the spacer to prevent ion implantation on the trench sidewall, such as severe process dispersion and high on-resistance.…”

Section: Introductionmentioning

confidence: 99%

Design of 1.2 kV SiC trench MOSFET using tilted ion implantation for suppression of electric field crowding at the bottom of the gate oxide

Park

Yoon

Kim

et al. 2023

Jpn. J. Appl. Phys.

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In this study, the effect of applying the tilted ion implantation process of a 1.2 kV SiC trench MOSFET on the electrical characteristics of the devices was investigated. P-shielding with tilted ion implantation protects both the sidewall and bottom of the trench from an electric field, enabling stable high-voltage operation, and the cell pitch can be reduced by using only one channel. Moreover, the tilted ion implantation process has the advantage of not requiring additional masks. For a comparative analysis, the tilt angle for ion implantation into the trench was changed in a TCAD simulation. A high breakdown voltage of 1617 V was achieved under an optimized tilt angle of 18.2°, and a low on-resistance of 2.9 mΩ-cm2 was obtained via structural optimization.

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Section: Introductionmentioning

confidence: 99%

Design of 1.2 kV SiC trench MOSFET using tilted ion implantation for suppression of electric field crowding at the bottom of the gate oxide

Park

Yoon

Kim

et al. 2023

Jpn. J. Appl. Phys.

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“…To relieve the peak E ox around the gate trench, some novel device structures to solve this problem have been reported in recent years. [9][10][11][12][13][14][15][16][17][18][19] A gate bottom p + shielded trench MOSFET (PS-TMOS) has been reported. [9][10][11][12][13] However, the R on,sp of the device will be significantly increased.…”

Section: Introductionmentioning

confidence: 99%

“…[9][10][11][12][13][14][15][16][17][18][19] A gate bottom p + shielded trench MOSFET (PS-TMOS) has been reported. [9][10][11][12][13] However, the R on,sp of the device will be significantly increased. A high performance SiC trench MOS-FET with double-trench was proposed by Rohm Inc. to reduce the high E ox around the bottom of the gate trench.…”

Section: Introductionmentioning

confidence: 99%

Low switching loss and increased short-circuit capability split-gate SiC trench MOSFET with p-type pillar

Shen

Wang²,

Li³

et al. 2023

Chinese Phys. B

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A split-gate SiC trench gate MOSFET with stepped thick oxide, source-connected split-gate (SG), and p-type pillar (p-pillar) surrounded thick oxide shielding region (GSDP-TMOS) is investigated by Silvaco TCAD simulations. The source-connected SG and p-pillar shielding regions are introduced to form an effective two-level shielding, which reduces the specific gate-drain charge (Q gd,sp) and the saturation current, thus reducing the switching loss and increasing the short-circuit capability. A p-pillar shielding region surrounded thick oxide efficiently protects gate oxide from peak electric field, thereby increasing the breakdown voltage (BV). Additionally, because of the high concentration on the n-type drift region, the electrons diffuse rapidly and the specific on-resistance (R on,sp) becomes smaller. In the end, compared with the bottom p+ shielded trench MOSFET (GP-TMOS), the Baliga figure of merit (BFOM, BV2/R on,sp) is increased by 169.6%, and the high-frequency figure of merit (HF-FOM, R on,sp×Q gd,sp) is significantly improved by 310%, respectively.

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“…Compared to SiC planar MOSFETs, SiC trench MOSFETs are more popular in the industry for their better tradeoff between on-resistance and breakdown voltage [6][7][8][9]. The most advanced 4H-SiC trench MOSFETs in the industry today are Infineon's asymmetric trench MOSFETs and Rohm's double trench MOSFETs [10][11][12]. Double trench MOSFETs (DT-MOSFET) are more favored because of their greater design flexibility and lack of process limitations for high-energy ion implantation [13][14][15][16].…”

Section: Introductionmentioning

confidence: 99%

A novel 4H-SiC multiple stepped SGT MOSFET with improved high frequency figure of merit

Zhang,

Luo,

et al. 2023

Phys. Scr.

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A novel 4H-SiC Multiple Stepped SGT MOSFET (MSGT-MOSFET) is presented and investigated utilizing TCAD simulations in this paper. We have quantitatively studied the characteristics of the device through simulation modeling and physical model calculations, and comparatively analyzed the performance and application prospects of this novel device. The gate-to-drain capacitance (Cgd) and gate-to-drain charge (Qgd) of the MSGT-MOSFET are significantly reduced in comparison with the double trench MOSFET (DT-MOSFET) and the conventional SGT MOSFET (CSGT-MOSFET), due to the reduction of the overlapping area of the split gate (SG) structure and drift region. Therefore, the obtained high frequency figure of merit (HF-FOM) defined as [Ron×Cgd] reduced by 23.9% compared with DT-MOSFET and CSGT-MOSFET. And the HF-FOM [Ron×Qgd] for the MSGT-MOSFET significantly decreased by 71% and 50%, respectively, compared to that of the DT-MOSFET and CSGT-MOSFET. Furthermore, the switching loss is also simulated and calculated. And the total switching loss of the proposed MSGT-MOSFET realizes 42.9% and 21.7% reduction in comparison with the DT-MOSFET and CSGT-MOSFET. The overall enhanced performances suggest that the MSGT-MOSFET is an excellent choice for high frequency power electronic applications.

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Quasisaturation Effect and Optimization for 4H-SiC Trench MOSFET With P+ Shielding Region

Cited by 7 publications

References 26 publications

Design of 1.2 kV SiC trench MOSFET using tilted ion implantation for suppression of electric field crowding at the bottom of the gate oxide

Design of 1.2 kV SiC trench MOSFET using tilted ion implantation for suppression of electric field crowding at the bottom of the gate oxide

Low switching loss and increased short-circuit capability split-gate SiC trench MOSFET with p-type pillar

A novel 4H-SiC multiple stepped SGT MOSFET with improved high frequency figure of merit

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