R&amp;D of a pixel sensor based on fully depleted SOI technology

Tsuboyama, T.; Arai, Y.; Fukuda, Koichi; Hara, K.; Hayashi, Hirokazu; Hazumi, M.; Ida, Jiro; Ikeda, Hirokazu; Ikegami, Y.; Ishino, H.; Kawasaki, T.; Kohriki, T.; Komatsubara, H.; Martin, E.; Miyake, H.; Mochizuki, A.; Ohno, Morifumi; Saegusa, Yuuji; Tajima, H.; Tajima, O.; Takahashi, T.; Terada, S.; Unno, Y.; Ushiroda, Y.; Varner, G.

doi:10.1016/j.nima.2007.07.111

Cited by 12 publications

(6 citation statements)

References 6 publications

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“…It has been with the availability of a commercial SOI process with small feature size CMOS from the collaboration between KEK, Tsukuba and OKI Industries Inc. that a systematic R&D effort on SOI pixel detectors has started [11,12]. The KEK-OKI process has special vias cut into the BOX to contact the underlying handle wafer and collect the charge signal.…”

Section: Introductionmentioning

confidence: 99%

Characterisation of a pixel sensor in SOI technology for charged particle tracking

Battaglia¹,

Bisello²,

Contarato³

et al. 2011

Nuclear Instruments and Methods in Physics Research Section A:

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This paper presents the results of the characterisation of a pixel sensor manufactured OKI 0.2 µm SOI technology integrated on a high-resistivity substrate, and featuring several pixel cell layouts for charge collection optimisation. The sensor is tested with short IR laser pulses, X-rays and 200 GeV pions. We report results on charge collection, particle detection efficiency and single point resolution.

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Section: Introductionmentioning

confidence: 99%

Characterisation of a pixel sensor in SOI technology for charged particle tracking

Battaglia¹,

Bisello²,

Contarato³

et al. 2011

Nuclear Instruments and Methods in Physics Research Section A:

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“…Through the KEK detector technology project [21], we fabricated the test circuits using 0.2-fully depleted silicon-on-insulator (SOI) technology provided by OKI Electric Industry [22]. Fig.…”

Section: A Test Circuitsmentioning

confidence: 99%

Waveform Observation of Digital Single-Event Transients Employing Monitoring >Transistor Technique

Kobayashi

Hirose

Yanagawa

et al. 2008

IEEE Trans. Nucl. Sci.

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Waveforms of digital single-event transients, radiation-induced voltage transients in logic gates, can be observed by connecting two transistors to a target logic gate. Additional transistors monitor voltage transients through their drain currents, which can be measured using the conventional 50-transmission-line technique widely used for measuring transient currents in single elementary transistors. Experimental results obtained in pulsedlaser irradiation tests demonstrate the validity of the observation technique and clearly reveal the pulse evolution as a function of the laser pulse energy.

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“…High speed, low power dissipation designs are thus possible, with improved latch-up immunity. A pioneering work by KEK led to the fabrication of prototype pixel chips with a 350 µm substrate, a 200 nm thin buried oxide and a 40 nm thin CMOS layer, which is fully depleted at operational voltages [36,37]. The functionality of the first prototype has been demonstrated in 2006, and has led to a second run where several institutions in Asia and in the US submitted their designs.…”

Section: Pos(vertex 2007)024mentioning

confidence: 99%