Radiant: efficient page table management for tiered memory systems

Kumar, Sandeep; Prasad, Aravinda; Sarangi, Smruti R.; Subramoney, Sreenivas

doi:10.1145/3459898.3463907

Cited by 7 publications

(5 citation statements)

References 26 publications

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“…We choose eight representative memoryintensive applications, including graph processing (Graph500, PageRank), an HPC workload (XSBench), machine learning (Liblinear), an in-memory database engine (Silo), an in-memory index lookup (Btree), and SPEC CPU 2017 (603.bwaves, 654.roms). These benchmarks are widely used to evaluate tiered memory systems [36,68], huge page management [26,38,57,67], and large memory servers [2,5,56]. Note that we choose only two benchmarks from SPEC CPU 2017 since they are the only ones that consume more than 10GB memory.…”

Section: Evaluation Methodologymentioning

confidence: 99%

“…Software-based tiered memory system. Prior softwarecontrolled tiered memory systems have explored the design space in various aspects including page migration [34,71,83,84], hotness detection [4,15,41], page replacement [28,48], and kernel object tiering [31,36] at different layers such as the application [29,44,69,79], library [21,54,68], and OS [14,27,30,32,76,78]. HotBox [14] suggests not using huge pages in tiered memory systems due to the hotness fragmentation in huge pages.…”

Section: Related Workmentioning

confidence: 99%

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MEMTIS: Efficient Memory Tiering with Dynamic Page Classification and Page Size Determination

Lee,

Monga,

Min

et al. 2023

Proceedings of the 29th Symposium on Operating Systems Principles

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The evergrowing memory demand fueled by datacenter workloads is the driving force behind new memory technology innovations (e.g., NVM, CXL). Tiered memory is a promising solution which harnesses such multiple memory types with varying capacity, latency, and cost characteristics in an effort to reduce server hardware costs while fulfilling memory demand. Prior works on memory tiering make suboptimal (often pathological) page placement decisions because they rely on various heuristics and static thresholds without considering overall memory access distribution. Also, deciding the appropriate page size for an application is difficult as huge pages are not always beneficial as a result of skewed accesses within them. We present Memtis, a tiered memory system that adopts informed decision-making for page placement and page size determination. Memtis leverages access distribution of allocated pages to optimally approximate the hot data set to the fast tier capacity. Moreover, Memtis dynamically determines the page size that allows applications to use huge pages while avoiding their drawbacks by detecting inefficient use of fast tier memory and splintering them if necessary. Our evaluation shows that Memtis outperforms state-of-the-art tiering systems by up to 169.0% and their best by up to 33.6%.CCS Concepts: • Software and its engineering → Memory management; • Computer systems organization → Heterogeneous (hybrid) systems.

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Section: Evaluation Methodologymentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

MEMTIS: Efficient Memory Tiering with Dynamic Page Classification and Page Size Determination

Lee,

Monga,

Min

et al. 2023

Proceedings of the 29th Symposium on Operating Systems Principles

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“…To understand whether these benefits hold in a disaggregated memory system, we pin the working set entirely in remote memory and configure the system to use huge pages. Page tables are placed in local memory for the best performance [6,29]. We compare huge and base page performance under varying remote memory latencies.…”

Section: Slow Remote Memory Renders Huge Pages Ineffectivementioning

confidence: 99%

Reconsidering OS memory optimizations in the presence of disaggregated memory

Bergman

Faldu

Grot

et al. 2022

Proceedings of the 2022 ACM SIGPLAN International Symposium on Memory Management

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Tiered memory systems introduce an additional memory level with higher-than-local-DRAM access latency and require sophisticated memory management mechanisms to achieve cost-efficiency and high performance. Recent works focus on byte-addressable tiered memory architectures which offer better performance than pure swap-based systems. We observe that adding disaggregation to a byte-addressable tiered memory architecture requires important design changes that deviate from the common techniques that target lowerlatency non-volatile memory systems. Our comprehensive analysis of real workloads shows that the high access latency to disaggregated memory undermines the utility of well-established memory management optimizations. Based on these insights, we develop HotBox -a disaggregated memory management subsystem for Linux that strives to maximize the local memory hit rate with low memory management overhead. HotBox introduces only minor changes to the Linux kernel while outperforming state-of-the-art systems on memory-intensive benchmarks by up to 2.25×. CCS Concepts:• Software and its engineering → Memory management; • Hardware → Emerging architectures.

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“…Memory accesses triggered by page walks can account for up to 20∼40% of total memory accesses [20]. Recent studies have pointed out that address translations requiring many memory accesses are the primary performance bottleneck [18], [29], [30], [33], [34], [42], [43].…”

Section: Emerging Workload Challengesmentioning

confidence: 99%

“…However, L2 TLB does not perform well on workloads with large memory footprints and irregular memory access patterns (bc-kron, bc-urand, bfs-kron, bfs-urand, and gups), and hence these workloads suffer from frequent L2 TLB misses. Due to the frequent misses on the L2 TLB, the fraction of page walks in total memory access latency becomes considerably high when these workloads are executed, resulting in a substantial decrease in system performance [15], [43], [44].…”

Section: Motivation a Tlb Missesmentioning

confidence: 99%

Pinning Page Structure Entries to Last-Level Cache for Fast Address Translation

2022

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As the memory footprint of emerging applications keeps increasing, the address translation becomes a critical performance bottleneck due to frequent misses on TLB. In addition, the TLB miss penalty becomes more critical in modern computer systems because the levels of the hierarchical page table (a.k.a. radix page table) are increasing to extend address space. In order to reduce the TLB misses, modern highperformance processors employ a multi-level TLB structure that uses a large last-level TLB. Employing a large last-level TLB might reduce the TLB misses. However, its capacity is still limited, and it can incur chip area overheads. In this paper, we propose a PSE Pinning mechanism that provides a large PSE (Page Structure Entry) store by dedicating some space of the last-level cache for only storing the page structure entries. PSE Pinning is based on three key observations. First, memory-intensive applications suffer from frequent misses on the last-level cache. Thus, most space of the last-level cache is not well utilized. Second, most PSEs are fetched from the main memory during the page table walk process, meaning the cache lines for the PSEs are frequently evicted from the on-chip caches. Lastly, a small number of PSEs are frequently accessed while others are not. By exploiting these three observations, PSE Pinning pins the frequently accessed page structure entries to the last-level caches so that they can reside on the cache. Experimental results show that PSE Pinning improves the performance of memory-intensive workloads suffering from frequent L2 TLB misses by 7.8% on average.

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Radiant: efficient page table management for tiered memory systems

Cited by 7 publications

References 26 publications

MEMTIS: Efficient Memory Tiering with Dynamic Page Classification and Page Size Determination

MEMTIS: Efficient Memory Tiering with Dynamic Page Classification and Page Size Determination

Reconsidering OS memory optimizations in the presence of disaggregated memory

Pinning Page Structure Entries to Last-Level Cache for Fast Address Translation

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