Radiation hardened by design techniques to reduce single event transient pulse width based on the physical mechanism

et al. 2017

This paper intends to present a novel radiation-hardened SRAM cell by using the PMOS transistors stacked (each PMOS is split into two same sizes) and changing the inner topological structure on basis of the Quatro-10T. Combined with layout-level optimization design, the 3-D TCAD mixed-mode simulation results show that the novel design has a great single event upset (SEU) immune. Simultaneously, it is found to be tolerant of partial single-event multiple-node upsets (SEMNUs) due to the charge sharing among off-PMOS transistors. In addition, compared with the Quatro-10T, our proposed structure exhibits larger static noise margin (SNM) as well as lower power consumption in 65 nm COMS technology.

“…The hardening technique by stacked transistor has been demonstrated according to the reference [7,11]. Thus, on the basis of original Quatro-10T cell in Fig.…”

Section: Proposed Circuitmentioning

confidence: 99%

Section: Proposed Circuitmentioning

confidence: 99%

A radiation harden enhanced Quatro (RHEQ) SRAM cell

Peng

Chen

et al. 2017

“…In common CMOS process, the radiation hardened by design (RHBD) layout methods have been proposed to enhance the SET tolerance [1,2,3,4,5,6,7]. Charge sharing techniques and SETs model are used to mitigate SET effects [8,9].…”

Section: Introductionmentioning

confidence: 99%

A single-event transient hardened LDO regulator with built-in filter

Ding

Liu

et al. 2015

A single-event transient (SET) hardened LDO using novel structure is proposed to enhance the single-event effect tolerance. The novel LDO with built-in filter can mitigate the response of the sensitive nodes of circuit. If the SET pulse current flows through the sensitive nodes, the maximum variation of the output voltage is only 15.5 mV. In addition, the transient performance is slightly dropped back as a tradeoff for the built-in filter. When the workload changes transiently between 100 µA and 100 mA in 100 ns, the undershoot is 28.4 mV and the overshoot is nearly 20 mV with imperceptible peak.

“…SET has already become one important concern for the radiation effect researchers [2], because SET in combinational logic circuit causes the system soft errors [3,4]. Nowadays, reliability is emerging as an important parameter in deep submicron electronic technologies.…”

Section: Introductionmentioning

confidence: 99%

An SET hardened dual-modular majority voter circuit for TMR system

Liu

Yan

2014

A Triple-modular redundancy (TMR) system will have a failure if Single Event Transient (SET) faults affect the voter. In this paper, we propose a full SET-tolerance dual-modular majority voter (DMV) circuit for all internal nodes. The DMV consisting of two simplex-modular voters, two inverters, a C-element inverter and a weak keeper is implemented in CMOS 40 nm technology. A novel XOR gate and a multiplexer based voter is also presented and used as a simplex-modular voter so that the whole DMV can be implemented by 40 CMOS transistors. A novel C-element weak keeper is also proposed to reduce power consumption. Monte-Carlo simulation results show that power consumption of DMV only increases by 11.09% compared to that of a single traditional voter.