Radiation-hardened library cell template and its total ionizing dose (TID) delay characterization in 65nm CMOS process

Abstract

We propose a radiation-hardened library cell template based on a 65nm CMOS process for the development of a radiation-hardened-by-design (RHBD) cell library for space and satellite (S&S) applications. The proposed library cell template adheres to the fixed-height variable-width standard cell approach, and is designed to inherently embody a number of RHBD techniques at the device-and layout-level to mitigate the radiation effects. We further design a test circuitry embodying several library cells based on the RHBD template for total ionizing dose (TID) irradiation testing. With the test circuitry, we show that our RHBD library cells experience insignificant delay effects at TID dosage up to 500Krad, V DD = 0.9V−1.4V. The irradiating tests provide concrete experimental data that verify the robustness of our proposed RHBD cell template and the ensuing design methodologies (including library development) for S&S electronics.

Single-Event-Transient Resilient Memory for DSP in Space Applications

“…The area of the SRAM cell is 6.2um × 4.45um. We also adopt the layout-level RHBD practices [17]- [18]to realize the TICE SRAM cells. Particularly, guard rings are used to mitigate single-event-latch-up and isolation.…”

“…The circuit level RHBD techniques include Dual-Interlocked-Cell (DICE) [9] and other RHBD memory cells [8]- [12]. The transistor/layout level includes transistor-up sizing, and special layout practices [3], [17]- [18]. These RHBD techniques generally incur overheads (than unhardened counterparts) and can enhance either SEUs or SETs but not both.…”