Total Ionizing Dose (TID) effects on finger transistors in a 65nm CMOS process

Abstract

Although Total Ionizing Dose (TID) effects are generally unpronounced in deep-submicron-CMOS, we show the TID-induced leakage current @TID=500Krad is significant in NMOS-finger-transistors of GlobalFoundries 65nm CMOS. Further, Radiation-Hardening-By-Design techniques against said TID effect are recommended. I.

Single-Event-Transient Resilient Memory for DSP in Space Applications

“…The area of the SRAM cell is 6.2um × 4.45um. We also adopt the layout-level RHBD practices [17]- [18]to realize the TICE SRAM cells. Particularly, guard rings are used to mitigate single-event-latch-up and isolation.…”

“…The circuit level RHBD techniques include Dual-Interlocked-Cell (DICE) [9] and other RHBD memory cells [8]- [12]. The transistor/layout level includes transistor-up sizing, and special layout practices [3], [17]- [18]. These RHBD techniques generally incur overheads (than unhardened counterparts) and can enhance either SEUs or SETs but not both.…”

Design and realization of low dropout voltage regulator and voltage reference in deep-submicron CMOS for emerging Internet-of-Things and satellites

“…However, the design of the RHBD CMOS voltage reference is challenging in the sense that the prevalent CMOS voltage references at this juncture (including the bandgap reference and the subthreshold voltage reference) are sensitive to TID effect [86]. This is because the TID effect deteriorates the characteristic of the BJT and MOSFET biased at subthreshold region [87,88]. For the bandgap reference, the TID effect is seriousit is severe even when the irradiation dose rate is lowthe phenomenon is known as the Enhanced Low Dose Rate Sensitivity (ELDRS) effect [89].…”

“…23 depicts the Id-Vg characteristics of an NMOS in GlobalFoundries 65nm CMOS under TID=0rad and 500krad[88]. FromFigure 2.23, it is interesting to note that although the deep submicron CMOS is largely free from the TID induced threshold voltage shift, the off-state current of the NMOS is undesirably increased due to the TID effect.…”

“…24 [88] depicts the cross-section view of an NMOS. Due to the presence of the thick STI SiO2 at the edge of the NMOS, the NMOS can be modeled as a combination of the main NMOS and a TID-susceptible parasitic NMOS[88]. The total drain current, Id_tot equals to the summation of the main NMOS current, Id_main, and the parasitic NMOS current, Id_par.…”