Radiation tolerant VLSI circuits in standard deep submicron CMOS technologies for the LHC experiments: practical design aspects

Anelli, G.; Campbell, M.; Delmastro, M.; Faccio, F.; Floria, S.; Giraldo, A.; Heijne, E.H.M.; Jarron, P.; Kloukinas, K.; Marchioro, A.; Moreira, P; Snoeys, W.

doi:10.1109/23.819140

Cited by 344 publications

(143 citation statements)

References 12 publications

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“…For many of the digital ASICs, a commercial DSM 0.25 µm CMOS technology with a radiation-tolerant layout technique was used [21,22]. The layouts made systematic use of an enclosed transistor topology and guard rings to prevent any radiation-induced leakage current under the thick isolation oxide.…”

Section: Some Methods Used To Improve Radiation Tolerancementioning

confidence: 99%

Radiation qualification of the front-end electronics for the readout of the ATLAS liquid argon calorimeters

et al. 2008

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The ATLAS detector has been built to study the reactions produced by the Large Hadron Collider (LHC). ATLAS includes a system of liquid argon calorimeters for energy measurements. The electronics for amplifying, shaping, sampling, pipelining, and digitizing the calorimeter signals is implemented on a set of front-end electronic boards. The front-end boards are installed in crates mounted between the calorimeters, where they will be subjected to significant levels of radiation during LHC operation. As a result, all components used on the front-end boards had to be subjected to an extensive set of radiation qualification tests. This paper describes radiationtolerant designs, radiation testing, and radiation qualification of the front-end readout system for the ATLAS liquid argon calorimeters.

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Section: Some Methods Used To Improve Radiation Tolerancementioning

confidence: 99%

Radiation qualification of the front-end electronics for the readout of the ATLAS liquid argon calorimeters

et al. 2008

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“…This cell has an area of 12.39 µm 2 , and has been designed to meet the requirements of most space applications. The use of conventional n-channel MOS transistors leads to an increase of leakage current in the latches, due to the total dose.…”

Section: Sram Cellsmentioning

confidence: 99%

“…A common solution to mitigate such effects is based on the design of circuit layout using n-channel Edge Less Transistors (ELTs), i.e., MOS transistors with edgeless shapes [2], [3]. Fig.…”

Section: Radiation Hardening-by-design Techniquesmentioning

confidence: 99%

Design of rad-hard SRAM cells: A comparative study

Benigni

Liberali

Stabile

et al. 2010

2010 27th International Conference on Microelectronics Proceedings

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Abstract-This paper presents the design of three static RAM cells, designed to be radiation hard. The memory cells are designed with three different approaches and layout styles. Three memory arrays, each of them made with a different cell, were designed and simulated to optimize the transistor sizes. The layout of the cells has been drawn, and parasitic elements were extracted to analyze their impact on circuit performance. Simulation results demonstrate that the three cells are functional in all worst case corners. The sensitivity of each cell to single events has been estimated using a fault injection technique. A silicon prototype employing the first cell has been fabricated and characterized.

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“…Previous approaches presented pseudo-empirical results as a function of technology dependent parameters that needed to be fitted to experimental data [4,6]. Moreover, Riemann's mapping theorem guarantees the existence of a univalent mapping of any device with a gate bonded by a simple closed curve to a rectangular device.…”

Section: An Accurate Strong-inversion Modelmentioning

confidence: 99%

A dc I–V model for short‐channel polygonal enclosed‐layout transistors

López

Hauer

Blanco-Filgueira

et al. 2008

Circuit Theory & Apps

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SUMMARYDespite the demonstrated radiation immunity of gate-enclosed layout transistors in deep submicron CMOS technologies, there is a significant lack of a thorough theoretical study addressing fundamental design issues on this kind of transistors. In this paper we propose a physical dc I -V model for short-channel polygonal-shape enclosed-layout transistors in both the linear and saturation regions of operation accounting for second-order effects such as depletion region non-uniformity, carrier velocity and channel length modulation. The impact of this layout style on the driving capability of the devices is also investigated. Experimental results based upon a fabricated NMOS test chip containing these devices in a standard 0.18 m CMOS technology process are presented. The comparison of the theoretical prediction with the experimental data show close agreement.

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Radiation tolerant VLSI circuits in standard deep submicron CMOS technologies for the LHC experiments: practical design aspects

Cited by 344 publications

References 12 publications

Radiation qualification of the front-end electronics for the readout of the ATLAS liquid argon calorimeters

Radiation qualification of the front-end electronics for the readout of the ATLAS liquid argon calorimeters

Design of rad-hard SRAM cells: A comparative study

A dc I–V model for short‐channel polygonal enclosed‐layout transistors

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