Random dopant induced threshold voltage lowering and fluctuations in sub-0.1 μm MOSFET's: A 3-D "atomistic" simulation study

Superlattices and Microstructures

et al. 2000

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A 3D statistical 'atomistic' simulation technique has been developed to study the effect of the random dopant induced parameter fluctuations in aggressively scaled MOSFETs. Efficient implementation of the 'atomistic' simulation approach has been used to investigate the threshold voltage standard deviation and lowering in the case of uniformly doped MOSFETs, and in fluctuation-resistant architectures utilising epitaxial-layers and delta-doping. The effect of the random doping in the polysilicon gate on the threshold voltage fluctuations has also been thoroughly investigated. The influence of a single-charge trapping on the channel conductivity in decanano MOSFETs is studied in the 'atomistic' framework as well. Quantum effects are taken into consideration in our 'atomistic' simulations using the density gradient formalism.

Section: Simulation Approachmentioning

confidence: 99%

Section: Classical Atomistic Simulationsmentioning

confidence: 99%

Section: Classical Atomistic Simulationsmentioning

confidence: 99%

Section: Simulation Approachmentioning

confidence: 99%

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Statistical 3D ‘atomistic’ simulation of decanano MOSFETs

Asenov

Slavcheva

Superlattices and Microstructures

et al. 2000

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“…A substantial amount of theoretical work has been done in studying the performance of trigate FETs and nanowires. This work ranges from semi-classical transport studies [4] to full-band quantum transport analysis [5].Substantial work on the impact of random discrete dopants on the performance of MOSFET transistors has been carried out [6][7][8][9][10]. This work has made use of Drift-diffusion, Monte Carlo and the Non-Equilibrium Green function (NEGF) carrier transport models.…”

mentioning

confidence: 99%

NEGF simulations of a junctionless Si gate-all-around nanowire transistor with discrete dopants

Martı́nez

Aldegunde

Solid-State Electronics

et al. 2012

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We have carried out 3D Non-Equilibrium Green Function simulations of a junctionless gate-all-around ntype silicon nanowire transistor of 4.2×4.2 nm 2 crosssection. We model the dopants in a fully atomistic way. The dopant distributions are randomly generated following an average doping concentration of 10 20 cm -3 . Elastic and inelastic Phonon scattering is considered in our simulation. Considering the dopants in a discrete way is the first step in the simulation of random dopant variability in junctionless transistors in a fully quantum mechanical way. Our results show that, for devices with an "unlucky" dopant configuration, with a starvation of donors under the gate, the threshold voltage can increase by a few hundred mV relative to devices with a more homogeneous distribution of dopants. IntroductionJunctionless Field Effect Transistors (JLFET) [1-2] have been proposed as an alternative to the standard minority-carrier channel MOSFETs at the end of the road map. As transistor dimensions scale down to tens of nanometres it became increasingly complicated to control the dopants at the source/channel and channel/drain boundaries. Another related problem is the intrinsic discreteness of dopants, which makes these boundaries less well defined at the nanoscale. As the JLFET is doped all the way through from source/channel/drain at the same doping concentration it is argued that it will not suffer of variability coming from fluctuations in the effective channel length, which becomes important at channel lengths of approximately 20 nm for conventional silicon transistors. Recently, a paper from the Tyndall Institute [3] has shown, experimentally and theoretically, the potential of the JLFET. A substantial amount of theoretical work has been done in studying the performance of trigate FETs and nanowires. This work ranges from semi-classical transport studies [4] to full-band quantum transport analysis [5].Substantial work on the impact of random discrete dopants on the performance of MOSFET transistors has been carried out [6][7][8][9][10]. This work has made use of Drift-diffusion, Monte Carlo and the Non-Equilibrium Green function (NEGF) carrier transport models.Gate-all-around (GAA) nanowire transistors have a superior electrostatic integrity compared with the standard planar MOSFET architecture. When the nanowire cross-section becomes smaller than 10 nm, quantum confinement becomes important and a proper description of the sub-bands is necessary in order to properly describe quantum capacitances and the quasi-1D density of states. Furthermore, at channel lengths of less than 20 nm the tunnelling component of the sourcedrain current cannot be neglected [11]. Semi-classical simulation based on a Boltzmann description of the transport cannot capture the source-drain tunnelling.In this work we use the NEGF formalism to carry out simulations of the transfer characteristics of a junctionless Si GAA nanowire transistor. We consider the impact of the random discrete dopants in the active region of the device. Th...

Implications of Imperfect Interfaces and Edges in Ultra-small MOSFET Characteristics

Asenov

Kaya

2002

phys. stat. sol. (b)

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PACS : 73.40.Qv; 85.30.De We use 3D statistical simulations to analyze the influence of imperfect interfaces and edges in sub-100 nm MOSFET characteristics. In particular, we focus on the impact of gates deformed by line edge roughness, and of oxide thickness variations resulting from a rough Si/SiO 2 interface. The 3D simulations are based on a very efficient 3D drift-diffusion framework, which can introduce quantum mechanical corrections via the density gradient formalism. Random features at the gate edges and at the Si/SiO 2 interface have similar statistical descriptions, but use different parameter sets in accordance with measurements. In MOSFETs, both line edge roughness and oxide thickness variations result in intrinsic parameter fluctuations, which are comparable in magnitude to random dopant effects. We simulate the dependence of intrinsic fluctuations on the statistical model parameters of the roughness. We also consider the scaling of devices with rough gate edges and rough SiO 2 interfaces. Our results highlight the importance of including realistic geometry features in the design and analysis of MOSFETs below 50 nm regime.