Rank-Aware Dynamic Migrations and Adaptive Demotions for DRAM Power Management

Lu, Yao; Wu, Donghong; He, Bingsheng; Tang, Xueyan; Xu, Jianliang; Guo, Minyi

doi:10.1109/tc.2015.2409847

Cited by 18 publications

(3 citation statements)

References 40 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Table 1 showcases most of the previously discussed works highlighting DRAM power savings in contrast to its respective additional hardware requirements. Due to the conventional structure of DRAM devices, most DRAM power or energysaving works are directed towards a rank-aware power management mechanism [5,31,9,13,12]. Only a handful of works are directed towards saving power from DRAM banks [10,19].…”

Section: Limitations Of Existing Workmentioning

confidence: 99%

VAR-DRAM: Variation-Aware Framework for Efficient Dynamic Random Access Memory Design

Goswami¹,

Mondal²,

Das³

et al. 2022

Preprint

View full text Add to dashboard Cite

Dynamic Random Access Memory (DRAM) is the de-facto choice for main memory devices due to its cost-effectiveness. It offers a larger capacity and higher bandwidth compared to SRAM but is slower than the latter. With each passing generation, DRAMs are becoming denser. One of its side-effects is the deviation of nominal parameters: process, voltage, and temperature. DRAMs are often considered as the bottleneck of the system as it trades off performance with capacity. With such inherent limitations, further deviation from nominal specifications is undesired. In this paper, we investigate the impact of variations in conventional DRAM devices on the aspects of performance, reliability, and energy requirements. Based on this study, we model a variation-aware framework, called VAR-DRAM, targeted for modern-day DRAM devices. It provides enhanced power management by taking variations into account. VAR-DRAM ensures faster execution of programs as it internally remaps data from variation affected cells to normal cells and also ensures data preservation. On extensive experimentation, we find that VAR-DRAM achieves peak energy savings of up to 48.8% with an average of 29.54% on DDR4 memories while improving the access latency of the DRAM compared to a variation affected device by 7.4%. Keywords DRAM • Process Variation • Power ManagementThe classic monolithic design of a typical DRAM has been enhanced to accommodate better performance in minimal power requirements. A modern-day DRAM device is organized into ranks and banks. Although this memory layer

show abstract

Section: Limitations Of Existing Workmentioning

confidence: 99%

VAR-DRAM: Variation-Aware Framework for Efficient Dynamic Random Access Memory Design

Goswami¹,

Mondal²,

Das³

et al. 2022

Preprint

View full text Add to dashboard Cite

show abstract

“…Existing research on demotions can be roughly divided into two categories: 1) how to make correct decisions on state transitions [7], [10], [13], [14], [21], and 2) how to extend the idle periods effectively [10], [15], [16], [21].…”

Section: Dram Demotionmentioning

confidence: 99%

Synergy of Dynamic Frequency Scaling and Demotion on DRAM Power Management: Models and Optimizations

Tang

et al. 2015

IEEE Trans. Comput.

Self Cite

View full text Add to dashboard Cite

Main memory (or DRAM) is one of the most significant components to the computer system's performance and energy consumption. Dynamic frequency scaling (DFS) and DRAM low-power states (Demotion) are two main-stream techniques for DRAM power management. DFS reduces the operation frequency of memory channels and DRAM devices when the memory bandwidth is under-utilized, whereas demotion transits individual memory ranks to low-power states during long idle periods. Despite that there have been fruitful research work for DFS and demotion separately, little attention has been paid to the synergy between these two techniques. To bridge this gap, this paper conducts a comprehensive study on the synergy between DFS and demotion. In particular, we leverage queuing theory to develop analytical models for the energy consumption and performance of DRAM systems with DFS and demotion. These models provide valuable insights into the synergy between DFS and demotion. We further attempt to minimize the energy consumption by considering both DFS and demotion while keeping a pre-defined performance penalty budget. To reduce the optimization complexity, we develop simple yet effective heuristics to search near-optimum DFS-demotion configurations. We experimentally compare our design with other state-of-the-art DRAM energy saving policies using detailed simulations of a large set of workloads. Experimental results show the accuracy of our analytical models and the effectiveness of our optimizations.Index Terms-Demotion, dynamic frequency scaling, energy consumption, main memory systems, in-memory processing Ç 1 INTRODUCTION E NERGY consumption has become a major factor in the design and implementation of modern computer systems. In many systems, main memory (or DRAM) is a critical component for the performance and energy consumption. As processors have moved to a multi-/many-core era, more applications run simultaneously with their working sets in the main memory. Emerging applications such as in-memory data analytics [1] and RAMCloud [2] boost the memory capacity of modern computing systems. Such hunger for main memory of larger capacity makes the amount of energy consumed by main memory approaching or even surpassing that consumed by processors in many servers [3], [4]. For example, it has been reported that main memory contributes to as much as 40-46 percent of total energy consumption in server applications [5], [6]. For these reasons, this paper investigates whether and how we can leverage DRAM power management techniques to reduce the energy consumption of main memory.There have been various energy saving techniques on exploiting the power management capability of main memory. Two important and common techniques are DRAM low-power states (Demotion) [7], [8], [9], [10] and dynamic frequency scaling (DFS) [11], [12]. The common theme of demotions is to transit individual memory ranks to low-power states during (long) idle periods, whereas DFS dynamically scales the operation frequency of memory channels and DRAM devices to make the...

show abstract

“…Although DRAM scal-ing is continued from 28 nm in 2013 to 10+ nm in 2016 [4,5] , the scaling has slowed down and become more and more difficult. Moreover, recent studies [6][7][8][9][10] have showed that DRAM-based main memory accounts for about 30%-40% of the total energy consumption of a physical server.…”

Section: Introductionmentioning

confidence: 99%

A Survey of Non-Volatile Main Memory Technologies: State-of-the-Arts, Practices, and Future Directions

Liu

Chen

Jin

et al. 2021

J. Comput. Sci. Technol.

View full text Add to dashboard Cite

Non-Volatile Main Memories (NVMMs) have recently emerged as a promising technology for future memory systems. Generally, NVMMs have many desirable properties such as high density, byte-addressability, non-volatility, low cost, and energy efficiency, at the expense of high write latency, high write power consumption, and limited write endurance. NVMMs have become a competitive alternative of Dynamic Random Access Memory (DRAM), and will fundamentally change the landscape of memory systems. They bring many research opportunities as well as challenges on system architectural designs, memory management in operating systems (OSes), and programming models for hybrid memory systems. In this article, we first revisit the landscape of emerging NVMM technologies, and then survey the state-of-the-art studies of NVMM technologies. We classify those studies with a taxonomy according to different dimensions such as memory architectures, data persistence, performance improvement, energy saving, and wear leveling. Second, to demonstrate the best practices in building NVMM systems, we introduce our recent work of hybrid memory system designs from the dimensions of architectures, systems, and applications. At last, we present our vision of future research directions of NVMMs and shed some light on design challenges and opportunities.

show abstract

Rank-Aware Dynamic Migrations and Adaptive Demotions for DRAM Power Management

Cited by 18 publications

References 40 publications

VAR-DRAM: Variation-Aware Framework for Efficient Dynamic Random Access Memory Design

VAR-DRAM: Variation-Aware Framework for Efficient Dynamic Random Access Memory Design

Synergy of Dynamic Frequency Scaling and Demotion on DRAM Power Management: Models and Optimizations

A Survey of Non-Volatile Main Memory Technologies: State-of-the-Arts, Practices, and Future Directions

Contact Info

Product

Resources

About