RapidMRC

Tam, David; Azimi, Reza; Soares, Livio; Stumm, Michael

doi:10.1145/1508244.1508259

Cited by 114 publications

(6 citation statements)

References 39 publications

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“…Modeling application interferences is challenging, and one way to address this problem is to partition the cache to avoid these potential interferences. Multiple CP schemes have been designed, through hardware techniques (Kim et al, 2004; Nesbit et al, 2007; Qureshi and Patt, 2006) and software techniques (Guan et al, 2009; Lin et al, 2008; Tam et al, 2007; Taylor et al, 1990). Most of the hardware approaches are efficient with a very low overhead at the execution time, but they suffer from an extra cost in terms of hardware components.…”

Section: Related Workmentioning

confidence: 99%

“…On the side of software-based solutions, the most popular is page coloring , where physical pages are selected for application allocations so that they end up in specific sections of the cache. Tam et al (2007) showed that important gains can be achieved through a static partitioning of the L2 cache using page coloring. Besides static strategies, dynamic CP strategies using page coloring have also been studied.…”

Section: Related Workmentioning

confidence: 99%

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Co-scheduling HPC workloads on cache-partitioned CMP platforms

Aupy

Benoît

Goglin

et al. 2019

The International Journal of High Performance Computing Applica

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With the recent advent of many-core architectures such as chip multiprocessors (CMPs), the number of processing units accessing a global shared memory is constantly increasing. Co-scheduling techniques are used to improve application throughput on such architectures, but sharing resources often generates critical interferences. In this article, we focus on the interferences in the last level of cache (LLC) and use the Cache Allocation Technology (CAT) recently provided by Intel to partition the LLC and give each co-scheduled application their own cache area. We consider m iterative HPC applications running concurrently and answer to the following questions: (i) How to precisely model the behavior of these applications on the cache-partitioned platform? and (ii) how many cores and cache fractions should be assigned to each application to maximize the platform efficiency? Here, platform efficiency is defined as maximizing the performance either globally, or as guaranteeing a fixed ratio of iterations per second for each application. Through extensive experiments using CAT, we demonstrate the impact of cache partitioning when multiple HPC applications are co-scheduled onto CMP platforms.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Co-scheduling HPC workloads on cache-partitioned CMP platforms

Aupy

Benoît

Goglin

et al. 2019

The International Journal of High Performance Computing Applica

View full text Add to dashboard Cite

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“…However, all of the proposed methods have to inspect all memory accesses and measure stack distance. Other works [29] have proposed hardware-accelerated stack distance collection. Liu and Mellor-Crummey [17] use a technique based on shadow profiling that forks off a redundant copy of an application, instrumented by Pin, to measure the stack distances for a selected set of references [17].…”

Section: Related Workmentioning

confidence: 99%

Directed Statistical Warming through Time Traveling

Nikoleris

Eeckhout

Hägersten

et al. 2019

Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture

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Improving the speed of computer architecture evaluation is of paramount importance to shorten the time-to-market when developing new platforms. Sampling is a widely used methodology to speed up workload analysis and performance evaluation by extrapolating from a set of representative detailed regions. Installing an accurate cache state for each detailed region is critical to achieving high accuracy. Prior work requires either huge amounts of storage (checkpoint-based warming), an excessive number of memory accesses to warm up the cache (functional warming), or the collection of a large number of reuse distances (randomized statistical warming) to accurately predict cache warm-up effects.This work proposes DeLorean, a novel statistical warming and sampling methodology that builds upon two key contributions: directed statistical warming and time traveling. Instead of collecting a large number of randomly selected reuse distances as in randomized statistical warming, directed statistical warming collects a select number of key reuse distances, i.e., the most recent reuse distance for each unique memory location referenced in the detailed region. Time traveling leverages virtualized fast-forwarding to quickly 'look into the future' -to determine the key cachelines -and then 'go back in time' -to collect the reuse distances for those key cachelines at near-native hardware speed through virtualized directed profiling.Directed statistical warming reduces the number of warm-up references by 30× compared to randomized statistical warming. Time traveling translates this reduction into a 5.7× simulation speedup. In addition to improving simulation speed, DeLorean reduces the prediction error from around 9% to around 3% on average. We further demonstrate how to amortize warm-up cost across multiple parallel simulations in design space exploration studies. Implementing DeLorean in gem5 enables detailed cycle-accurate simulation at a speed of 126 MIPS. CCS CONCEPTS• Computing methodologies → Modeling and simulation; • Hardware → Analysis and design of emerging devices and systems; • Computer systems organization → Serial architectures.

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“…[Bennett and Kruskal(1975)]. Because of the overhead of the algorithm and the need to detect all memory accesses, it can only be used on-line when hardware support is available [Zhou et al(2004)], when large blocks are accessed explicitly [Kim et al(2000)], or when approximations are acceptable [Tam et al(2009),Zhou et al(2004]. In our caching middleware, we consider a single-level memory hierarchy (main memory), blocks (objects) that are accessed explicitly by calling the middleware, and use LRU as the object replacement policy.…”

Section: Cooperative Cachingmentioning

confidence: 99%

Barely Alive Servers: Greener Datacenters Through Memory-Accessible, Low-Power States

Anagnostopoulou

Biswas

Saadeldeen

et al. 2013

Design Technologies for Green and Sustainable Computing Systems

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Current resource provisioning schemes in Internet services leave servers less than 50% utilized almost all the time. At this level of utilization, the servers' energy efficiency is substantially lower than at peak utilization. A solution to this problem could be dynamically consolidating workloads into fewer servers and turning others off. However, services typically resist doing so, because of high response times during re-activation in handling traffic spikes. Moreover, services often want the memory and/or storage of all servers to be readily available at all times.In this paper, we propose a family of barely-alive active low-power server states that facilitates both fast re-activation and access to memory while in a low-power state. We compare these states to previously proposed active and idle states. In particular, we investigate the impact of load bursts in each energy-saving scheme. We also evaluate the additional benefits of memory access under low-power states with a study of a search service using a cooperative main-memory cache. Finally, we further investigate our barely-alive states in two case studies: (1) a mixed system that combines a barely-alive state with the off state to maximize energy savings; and (2) a barely-alive system that facilitates hosting more than one service at the same time. We find that the barely-alive states can reduce service energy consumption by up to 38%, compared to an energy-oblivious system. These energy savings are consistent across a large parameter space. In the presence of two services, the barely-alive system can reduce energy consuption by 34% over a two-system deployment.

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RapidMRC

Cited by 114 publications

References 39 publications

Co-scheduling HPC workloads on cache-partitioned CMP platforms

Co-scheduling HPC workloads on cache-partitioned CMP platforms

Directed Statistical Warming through Time Traveling

Barely Alive Servers: Greener Datacenters Through Memory-Accessible, Low-Power States

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