RAPPID: an asynchronous instruction length decoder

Abstract

This paper describes an investigation of potential advantages and risks of applying an aggressive asynchronous design methodology to Intel Architecture. RAPPID ("Revolving Asynchronous Pentium® Processor Instruction Decoder"), a prototype IA32 instruction length decoding and steering unit, was implemented using self-timed techniques. RAPPID chip was fabricated on a 0.25µ CMOS process and tested successfully. Results show significant advantages-in particular, performance of 2.5-4.5 instructions/nS-with manageable risks using this design technology. RAPPID achieves three times the throughput and half the latency, dissipating only half the power and requiring about the same area as an existing 400MHz clocked circuit.

Practical advances in asynchronous design and in asynchronous/synchronous interfaces

“…A research group at Intel demonstrated this with their asynchronous instruction length decoder design called RAPPID ("Revolving Asynchronous Pentium Processor c Instruction Decoder") [60]. The RAPPID's length decoding out-performs, by a factor of 3, the same function inside a 400MHz Pentium II fabricated in the identical 0.25µm CMOS process.…”

“…Work at Sun Labs [15] shows that asynchronous pipelines, if designed properly, can approach the speed of synchronous shift registers. However, it is unclear if asynchronous pipelines, except in some special cases [60], can ever out-perform synchronous counterparts. A goal is therefore to aim for comparable performance as a synchronous pipeline, but with the added benefits of "elasticity" (variable rate operation).…”

“…Burstmode CAD tools have been applied to several industrial designs, including an experimental routing chip [17] and low-power infrared communications chip [40] at HP Laboratories, an experimental SCSI controller at AMD [81], and a high-performance experimental instruction-length decoder at Intel [60].…”

Efficient performance analysis of asynchronous systems based on periodicity

“…One potential advantage of asynchronous systems over their clocked counterparts, in certain applications, is better average-case performance [1,19,25]. However, the performance analysis of asynchronous systems remains a challenge.…”

Area Optimizations for Dual-Rail Circuits Using Relative-Timing Analysis

“…To reduce these overheads, we propose using relative-timing analysis [15] to optimize these asynchronous implementations by reducing the size of the CD logic. One such system where relative-timing optimizations played a crucial role is the Intel Asynchronous InstructionLength Decoder [13], which was several times faster than its synchronous counterpart. This paper introduces several novel relative-timing algorithms that optimize asynchronous circuits for area.…”