Real Processing-in-Memory with Memristive Memory Processing Unit (mMPU)

Kvatinsky, Shahar

doi:10.1109/asap.2019.00-10

Cited by 15 publications

(12 citation statements)

References 66 publications

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“…2 2.5 pJ 5.8 pJ Tech. 3 2.2 pJ 4.2 pJ Tech. 4 5.94 pJ The proposed solution strongly outperforms different CMOS FA solutions [40-42] (>10 6 improvement in EDP) when VNB data exchange overhead [39] is included.…”

Section: Energy Fa Minmentioning

confidence: 99%

“…When accumulating a sequence of bits, all the bits are input sequentially to the HA representing the LSB. The operations of the subsequent HAs are performed only after a number of input bits equal to their relative bit position have been summed (e.g., HA with bit position 3 is activated only after 2 3 input bits have been summed). Thus, the length of the HA chain grows as more input bits have been summed.…”

Section: Binarized Neural Network Applicationsmentioning

confidence: 99%

“…From this standpoint, edge computing ensures a decrease in the amount of data to be exchanged, relaxing data transfer and power constraints with obvious benefits for consumer and industrial Internet of Things (IoT), smart cities, artificial intelligence (AI), machine learning, and 5G industry. Still, its implementation requires ultra-low power hardware solutions, mainly hindered by the von Neumann bottleneck (VNB) [1][2][3], i.e., the slow and energy-hungry data transfer between CPUs and off-chip non-volatile memories. As suggested in the latest IRDS report [4], logic-in-memory (LIM) architectures that allow executing Boolean operations directly inside the memory could circumvent the VNB.…”

Section: Introductionmentioning

confidence: 99%

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Multi-Input Logic-in-Memory for Ultra-Low Power Non-Von Neumann Computing

Zanotti¹,

Pavan²,

Puglisi³

2021

Micromachines

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Logic-in-memory (LIM) circuits based on the material implication logic (IMPLY) and resistive random access memory (RRAM) technologies are a candidate solution for the development of ultra-low power non-von Neumann computing architectures. Such architectures could enable the energy-efficient implementation of hardware accelerators for novel edge computing paradigms such as binarized neural networks (BNNs) which rely on the execution of logic operations. In this work, we present the multi-input IMPLY operation implemented on a recently developed smart IMPLY architecture, SIMPLY, which improves the circuit reliability, reduces energy consumption, and breaks the strict design trade-offs of conventional architectures. We show that the generalization of the typical logic schemes used in LIM circuits to multi-input operations strongly reduces the execution time of complex functions needed for BNNs inference tasks (e.g., the 1-bit Full Addition, XNOR, Popcount). The performance of four different RRAM technologies is compared using circuit simulations leveraging a physics-based RRAM compact model. The proposed solution approaches the performance of its CMOS equivalent while bypassing the von Neumann bottleneck, which gives a huge improvement in bit error rate (by a factor of at least 108) and energy-delay product (projected up to a factor of 1010).

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Section: Energy Fa Minmentioning

confidence: 99%

Section: Binarized Neural Network Applicationsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Multi-Input Logic-in-Memory for Ultra-Low Power Non-Von Neumann Computing

Zanotti¹,

Pavan²,

Puglisi³

2021

Micromachines

View full text Add to dashboard Cite

show abstract

“…Half‐select voltages ( V HS ), row/column isolation voltages ( V ISO ) and row‐grounding techniques [8, 28, 30] have been used in this work during the write, execution and read operations, respectively, to handle the undesired issues like write‐disturb, unwanted computing and sneak path problems [8, 21–24, 29].…”

Section: Proposed and Existing Memristive‐mappings Of A Bdd‐node Desmentioning

confidence: 99%

Binary decision diagram‐based synthesis technique for improved mapping of Boolean functions inside memristive crossbar‐slices

Chakraborty

Maurya

Prasad

et al. 2020

IET Computers & Digital Tech

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Memristors are two‐terminal nano‐electronic devices that make it possible to design non‐volatile memory and logic circuits with high integration density. The logic operations of memristor‐based circuits are performed by applying suitable voltages across them. Researchers have been widely experimenting with this device to efficiently implement particular logic functions. However, recently, a synthesis methodology for arbitrary logic functions has been reported, where an input Boolean function is first represented as a Binary Decision Diagram (BDD), followed by the mapping of the BDD‐nodes (netlists of 2‐input NOR and NOT gates) inside a cluster of sliced crossbar‐arrays. The authors propose to map the BDD‐nodes for any input Boolean function to the crossbar‐slices using an improved technique, where each BDD‐node is mapped more efficiently, and the node‐logic is implemented following the Memristor Aided loGIC (MAGIC) design style. Our proposed mapping‐based realization of a BDD‐node has superior performance and energy‐efficiency than the existing IMPLY and MAGIC‐based BDD‐node designs techniques, provided all three node‐designs are implemented inside the similar‐sized crossbars. Comparative‐study of the synthesis results showed that the memristive‐circuits generated using our proposed technique are 26.95% faster, and need 42.32% lesser memristors (on average) than their peers, implemented using the existing approach of slicing crossbar‐architecture.

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“…The Internet of Things (IoT) is promoting the spreading of battery powered smart devices in many sectors, from the industry, to improve the efficiency of industrial processing, to the healthcare, to monitor patients from distance, and in many others. This trend is posing a particular interest in the research of innovative solutions that enable the computation of logic operations directly inside the memory [1], [2], with the aim of bypassing the strongest limitation affecting traditional architectures, i.e., the data transfer between the memory and the CPU, also known as the von Neumann bottleneck [3]. Among emerging technologies, Resistive Random Access Memories (RRAM) are indeed a promising candidate for Logic-in-Memory (LIM) applications, as they are non-volatile storing elements which at the same time can also act as computing element in logic gates [4], [5].…”

Section: Introductionmentioning

confidence: 99%

Smart Logic-in-Memory Architecture for Low-Power Non-Von Neumann Computing

Zanotti

Puglisi

Pavan

2020

IEEE J. Electron Devices Soc.

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Low-power smart devices are becoming pervasive in our world. Thus, relevant research efforts are directed to the development of innovative low power computing solutions that enable inmemory computations of logic-operations, thus avoiding the von Neumann bottleneck, i.e., the known showstopper of traditional computing architectures. Emerging non-volatile memory technologies, in particular Resistive Random Access memories, have been shown to be particularly suitable to implement logic-in-memory (LIM) circuits based on the material implication logic (IMPLY). However, RRAM devices non-idealities, logic state degradation, and a narrow design space limit the adoption of this logic scheme. In this work, we use a physics-based compact model to study an innovative smart IMPLY (SIMPLY) logic scheme which exploits the peripheral circuitry embedded in ordinary IMPLY architectures to solve the mentioned reliability issues, drastically reducing the energy consumption and setting clear design strategies. We then use SIMPLY to implement a 1-bit full adder and compare the results with other LIM solutions proposed in the literature.

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Real Processing-in-Memory with Memristive Memory Processing Unit (mMPU)

Cited by 15 publications

References 66 publications

Multi-Input Logic-in-Memory for Ultra-Low Power Non-Von Neumann Computing

Multi-Input Logic-in-Memory for Ultra-Low Power Non-Von Neumann Computing

Binary decision diagram‐based synthesis technique for improved mapping of Boolean functions inside memristive crossbar‐slices

Smart Logic-in-Memory Architecture for Low-Power Non-Von Neumann Computing

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