Real-Time Discrete SPAD Array Readout Architecture for Time of Flight PET

Abstract

Single photon avalanche diode (SPAD) arrays have proven themselves as serious candidates for time of flight positron emission tomography (PET). Discrete SPAD readout schemes mitigate the low-noise requirements of analog schemes and offer very fine control over threshold levels and timing pickup strategies. On the other hand, a high optical fill factor is paramount to timing performance in such detectors, and consequently space is limited for closely integrated electronics. Nonetheless, a production, daily used PET scanner must minimize bandwidth usage, data volume, data analysis time and power consumption and therefore requires a real-time readout and data processing architecture as close to the detector as possible. We propose a fully digital, embedded real-time readout architecture for SPAD-based detector. The readout circuit is located directly under the SPAD array instead of within or beside it to overcome the fill factor versus circuit capabilities tradeoff. Since the overall real-time engine provides all the required data processing, the system needs only to send the data required by the PET coincidence engine, significantly reducing the bandwidth requirement. A 3D prototype device was implemented in 2 tiers of 130 nm CMOS from Global Foundry / Tezzaron featuring individual readout for 6 scintillator channels. The timing readout is provided by a first photon discriminator and a 31 ps resolution time to digital converter, while energy readout and event packaging is done in real-time using synchronous logic from a CMOS standard cell library, all fully embedded in the ASIC. The dedicated serial output line supports a sustained rate 2.2 Mcps in PET acquisition mode, or 170 kcps in an oscilloscope mode for offline validation and development.Index Terms-3D CMOS, CMOS, data acquisition system, digital readout, positron emission tomography, real-time processing, single photon avalanche diode, single photon timing resolution, SPAD, vertical integration.

Dark Count Impact for First Photon Discriminators for SPAD Digital Arrays in PET

“…var. jitter among all possible SPAD sources [14]. Input signals to the OR tree were seen as single 400 ps pulses, triggered once per photon detection.…”

“…It is an equivalent model to the data acquisition system (DAQ) presented in [14], simplified for simulation speed. The decision tree is summarized in Fig.…”

“…An alternative is to place the smart circuitry under the SPAD array with a 3D stack, as done for the HL-LHC/Atlas pixel detector [13] and emerging PET detector architectures [14].…”

High dynamic range readout architecture for SPAD array

“…The choice of using an analog counter in the readout circuit is based on several constraints, mainly the pixel fill factor. Therefore there are several readout architectures based on digital counters, but these architectures require a much larger surface area of pixel than analog architectures [6]. For example, using the AMS 0,35µm CMOS technology, a 7-bit digital counter requires a surface of 3300µm 2 , while an analog counter necessitates a surface of 230µm 2 [4].…”

Development of a data acquisition architecture with distributed synchronization for a Positron Emission Tomography system with integrated front-end.

“…• Increasingly complex local digital processing in FPGA [323,327,356] or, lately, integrated with the photodetector [220,368].…”