Single photon avalanche diode (SPAD) arrays have proven themselves as serious candidates for time of flight positron emission tomography (PET). Discrete SPAD readout schemes mitigate the low-noise requirements of analog schemes and offer very fine control over threshold levels and timing pickup strategies. On the other hand, a high optical fill factor is paramount to timing performance in such detectors, and consequently space is limited for closely integrated electronics. Nonetheless, a production, daily used PET scanner must minimize bandwidth usage, data volume, data analysis time and power consumption and therefore requires a real-time readout and data processing architecture as close to the detector as possible. We propose a fully digital, embedded real-time readout architecture for SPAD-based detector. The readout circuit is located directly under the SPAD array instead of within or beside it to overcome the fill factor versus circuit capabilities tradeoff. Since the overall real-time engine provides all the required data processing, the system needs only to send the data required by the PET coincidence engine, significantly reducing the bandwidth requirement. A 3D prototype device was implemented in 2 tiers of 130 nm CMOS from Global Foundry / Tezzaron featuring individual readout for 6 scintillator channels. The timing readout is provided by a first photon discriminator and a 31 ps resolution time to digital converter, while energy readout and event packaging is done in real-time using synchronous logic from a CMOS standard cell library, all fully embedded in the ASIC. The dedicated serial output line supports a sustained rate 2.2 Mcps in PET acquisition mode, or 170 kcps in an oscilloscope mode for offline validation and development.Index Terms-3D CMOS, CMOS, data acquisition system, digital readout, positron emission tomography, real-time processing, single photon avalanche diode, single photon timing resolution, SPAD, vertical integration.

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To increase contrast in positron emission tomography (PET) images, researchers are investigating detectors that reach below the nanosecond timing resolution. This allows a tight coincidence window which reduces random coincidence counts in the acquired data, as well as to include time-of-flight information into the reconstruction algorithms. With this goal in mind, single photon avalanche diode (SPAD) arrays have been under study for their excellent timing performances. However, their spurious dark counts can blur the start of PET signals where timing information is the most precise and create false starts in the acquisition system, introducing dead time. To minimize these problems in digital SPAD systems using a single time to digital converter (TDC) per PET channel, dark count discriminator circuits are required to reduce timing errors and increase the triggering efficiency in presence of dark counts. This paper compares the performance of a probabilistic and a novel delay line based dark count discriminator. Simulations of a SPAD array investigate the impact of dark counts on triggering efficiency and coincidence timing. Results show that the probabilistic discriminator provides excellent event recovery with regard to dark counts at the cost of some coincidence timing resolution. On the other hand, the delay line discriminator maintains the peak coincidence timing resolution but does not provide as much efficiency at high dark count rate levels.Index Terms-CMOS, dark count rate, digital readout, first photon discriminator, integrated circuits, photodetector, positron emission tomography (PET), scintillation detector, single photon avalanche diode (SPAD), time-of-flight, timing resolution.

Single photon avalanche diode (SPAD) arrays have proven themselves as serious candidates for time of flight positron emission tomography (PET). Discreet readout schemes mitigate the low-noise requirements of analog schemes and offer very fine control on threshold levels and timing pickup strategies. A high optical fill factor is paramount to timing performance in such detectors, and therefore space is limited for closely integrated electronics. On the other hand, a production, daily used PET scanner must minimize bandwidth usage, data volume, data analysis time and power consumption, and therefore requires a real-time readout and data processing architecture as close to the detector as possible.We propose a vertically integrated architecture that allows placement of the real-time data extraction directly under the detector while maintaining high optical fill factor for optimal timing performance. This paper focuses on the real-time data acquisition engine. It reduces transmitted data by a factor of 8 in standard operational mode. Combined with small local memory buffers, this significantly reduces acquisition dead time. Finally, auxiliary circuits accelerate channel self-diagnosis, essential for large PET systems.A prototype device featuring individual readout for 6 scintillator channels was fabricated. Timing readout is provided by a first photon discriminator driving a TDC, while energy reading and event packaging is done using standard logic. The dedicated serial output line supports a sustained rate of 170k counts per second (cps) in waveform mode, while the standard operational mode supports 2.2M cps. In normal PET acquisition conditions (up to 1250 cps/mm²), this provides ample bandwidth for more than 4 x 4 cm 2 detector surface.

CMOS integrated SPAD array design normally enforces a compromise between circuit functionalities and optical detection fill factor, never quite reaching the ideal detector configuration when both are integrated together on the same substrate. The emergence of vertical 3D integrated circuits (3DIC) changes this restriction and further adds in heterogeneous electronic integration, opening technological combinations otherwise difficult or impractical to obtain. Using this approach, a heterogeneous SPAD array detector prototype with digital readout for small animal PET was developed. It is based on Global Foundries 130 nm CMOS for digital and quenching circuits and on Teledyne Dalsa 0.8 µm HV CMOS process for the SPAD arrays. This paper focuses on the realtime digital architecture tailored for small animal PET scintillation detection, where in addition to tight timing and energy resolution, low PET dead time and high spatial resolution are required. A discriminator circuit is proposed to retain firstphoton timing information while protecting against dark count rate triggering. The system provides two operational modes: a slower oscilloscope-like mode and a high rate PET mode providing 2.2M singles per second on a single 200 MHz LVDS transmitter. Performances in terms of electronic jitter and event detection are reported based on simulations.