Single Photon Avalanche Diodes (SPAD) are known for their excellent timing performance which enables Time of Flight capabilities in positron emission tomography (PET). However, current array architectures juxtapose the SPAD with its ancillary electronics at the expense of a poor fill factor of the SPAD array. The 3D vertical integration of SPADs and readout electronics represents a solution to the aforementioned problem. Compared to systems with external electronics readout, 3D vertical integration reduces the SPAD interconnect parasitic capacitance while greatly increasing the photosensitive area and improving overall performances. This paper presents the implementation of two SPAD structures designed for PET. The SPAD structures are designed using Teledyne DALSA high voltage (HV) CMOS technology targeted for a 3-dimensional single photon counting module (3DSPCM). SPAD with two types of guard ring (diffusion-based and virtual guard ring) are designed, fabricated and characterized. All structures are based on a anode in an -well cathode and are implemented along with active quenching circuits for proper characterization. The results show that the contact distribution and the anode-cathode spacing impact the dark count rate (DCR). The design of SPADs with a diffusion guard ring have a DCR down to s m at room temperature, afterpulsing probability of , timing resolution of 27 ps FWHM and PDE of 49% at 480 nm.

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To increase contrast in positron emission tomography (PET) images, researchers are investigating detectors that reach below the nanosecond timing resolution. This allows a tight coincidence window which reduces random coincidence counts in the acquired data, as well as to include time-of-flight information into the reconstruction algorithms. With this goal in mind, single photon avalanche diode (SPAD) arrays have been under study for their excellent timing performances. However, their spurious dark counts can blur the start of PET signals where timing information is the most precise and create false starts in the acquisition system, introducing dead time. To minimize these problems in digital SPAD systems using a single time to digital converter (TDC) per PET channel, dark count discriminator circuits are required to reduce timing errors and increase the triggering efficiency in presence of dark counts. This paper compares the performance of a probabilistic and a novel delay line based dark count discriminator. Simulations of a SPAD array investigate the impact of dark counts on triggering efficiency and coincidence timing. Results show that the probabilistic discriminator provides excellent event recovery with regard to dark counts at the cost of some coincidence timing resolution. On the other hand, the delay line discriminator maintains the peak coincidence timing resolution but does not provide as much efficiency at high dark count rate levels.Index Terms-CMOS, dark count rate, digital readout, first photon discriminator, integrated circuits, photodetector, positron emission tomography (PET), scintillation detector, single photon avalanche diode (SPAD), time-of-flight, timing resolution.