Real Time Image Rotation Using Dynamic Reconfiguration

Bourennane, El-Bay; Milan, Claude; Paindavoine, Michel; Bouchoux, Sophie

doi:10.1006/rtim.2002.0274

Cited by 7 publications

(16 citation statements)

References 18 publications

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“…1 The first represents the implementation cost and the second its performance. The cost is designated here by the number of configurable logic blocks, or CLBs ͑Cost CLB = N Stat_CLB = computation cells+ control cells͒ used to implement the algorithm.…”

Section: Criteria Analysis Of Static and Dynamicmentioning

confidence: 99%

Application based on dynamic reconfiguration of field-programmable gate arrays: JPEG 2000 arithmetic decoder

Bouchoux

Bourennane

2005

Opt. Eng.

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This paper describes the implementation of a part of the JPEG 2000 algorithm ͑MQ decoder and arithmetic decoder͒ on a fieldprogrammable gate array ͑FPGA͒ board by using dynamic reconfiguration. A comparison between static and dynamic reconfiguration is presented, and new analysis criteria ͑spatiotemporal efficiency, logic cost, and performance time͒ have been defined. The MQ decoder and arithmetic decoder are attractive for dynamic reconfiguration implementation in applications without parallel processing. This implementation is done on an architecture designed to study the dynamic reconfiguration of FPGAs: the ARDOISE architecture. The obtained implementation, based on four partial configurations of the arithmetic decoder, allows one to reduce the number of logic cells significantly ͑by 57%͒ in comparison with static implementation. © 2005 Society of Photo-Optical Instrumentation Engineers.

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Section: Criteria Analysis Of Static and Dynamicmentioning

confidence: 99%

Application based on dynamic reconfiguration of field-programmable gate arrays: JPEG 2000 arithmetic decoder

Bouchoux

Bourennane

2005

Opt. Eng.

Self Cite

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“…In order to validate the efficiency of the proposed DPR design flow and environment, image and signal processing algorithms for adaptive applications have been chosen as a targeted system to be deployed. Several approaches reveal the advantages of DPR in image and signal processing, including FPGA-based discrete cosine transform (DCT) architecture [7,13], real-time image interpolation [8,9], dynamic image processor [10] and advanced encryption standard (AES) [12]. However, there is no existing work reported on specific IP cores such as CSC, DBWT and HWT that can be used in image and signal processing for adaptive applications.…”

Section: Dpr Design Flow and Environmentmentioning

confidence: 99%

“…DPR has been widely studied in various fields [4][5][6][7][8][9][10][11][12][13][14][15][16][17][18]. However, current DPR design flows and implementations are not capable to provide a set of programs to establish communication between the FPGA and host computer.…”

Section: Introductionmentioning

confidence: 99%

An efficient FPGA-based dynamic partial reconfiguration design flow and environment for image and signal processing IP cores

Krill¹,

Ahmad²,

Amira³

et al. 2010

Signal Processing: Image Communication

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“…Lately, digital video surveillance systems have become a high-priority topic of research worldwide [6,16,36,37,40,45,69,98,149,155]. Relevant technologies include automatic, robust face recognition [11,28,92,112,146], gesture recognition [111,142], tracking of human or object movement [9,40,61,68,76,92,102,151], distributed or networked video surveillance with multiple cameras [17,37,53,75], etc.…”

Section: Growth In Applications Of Real-time Image/video Processingmentioning

confidence: 99%

“…This configuration is useful for reducing system size of embedded devices. The interested reader can refer to [2,14,22,83,140] for more information on run-time reconfigurations of FPGAs for image/video processing applications.…”

Section: Field Programmable Gate Arraysmentioning

confidence: 99%

Real-Time Image and Video Processing: From Research to Reality

Kehtarnavaz¹,

Gamadia²

2006

Synthesis Lectures on Image, Video, and Multimedia Processing

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This book presents an overview of the guidelines and strategies for transitioning an image or video processing algorithm from a research environment into a real-time constrained environment. Such guidelines and strategies are scattered in the literature of various disciplines including image processing, computer engineering, and software engineering, and thus have not previously appeared in one place. By bringing these strategies into one place, the book is intended to serve the greater community of researchers, practicing engineers, industrial professionals, who are interested in taking an image or video processing algorithm from a research environment to an actual real-time implementation on a resource constrained hardware platform. These strategies consist of algorithm simplifications, hardware architectures, and software methods. Throughout the book, carefully selected representative examples from the literature are presented to illustrate the discussed concepts. After reading the book, the readers are exposed to a wide variety of techniques and tools, which they can then employ for designing a real-time image or video processing system of interest. KEYWORDSReal-time image and video processing, Real-time implementation strategies, Algorithmic simplifications for real-time image and video processing, Hardware platforms for real-time image and video processing, Software methods for real-time image and video processing v

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Real Time Image Rotation Using Dynamic Reconfiguration

Cited by 7 publications

References 18 publications

Application based on dynamic reconfiguration of field-programmable gate arrays: JPEG 2000 arithmetic decoder

Application based on dynamic reconfiguration of field-programmable gate arrays: JPEG 2000 arithmetic decoder

An efficient FPGA-based dynamic partial reconfiguration design flow and environment for image and signal processing IP cores

Real-Time Image and Video Processing: From Research to Reality

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