Realization of Pb1Free FCiBGA Technology on Lowik Device

Hayashi, Eiji; Baba, Shinji; Idaka, Shiori; Maeda, Ayumi; Satoh, Mitsutaka; Kimura, M.

doi:10.1109/ectc.2005.1441237

Cited by 11 publications

(3 citation statements)

References 2 publications

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“…Results of a Pbfree qualification with 90nm device were presented last year for a 4-2-4 build-up laminate package (3). It is common knowledge in the industry that in addition to Pb-free bumping and organic package requirements, low-k dielectrics are required for high-performance devices in the 90nm and tighter device ground rules (1,2). We present results of a Pbfree CPI technology qualification of 200um pitch bumps on a 65nm device with low-k wiring on a thin-core 2-2-2 laminate package.…”

Section: Introductionmentioning

confidence: 97%

Qualification of Low-k 65nm Technology Die with Pb-free Bumps on a 2-2-2 Laminate Package (PBGA) with Pb-free Assembly Processes

Ray

Muncy

McLaughlin

et al. 2007

2007 Proceedings 57th Electronic Components and Technology Conference

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Flip-chip carriers have become the preferred solution for high-performance ASIC and microprocessor devices. Typically these are packaged in organic or ceramic Ball Grid Array (BGA) connections. Recently, there has been a significant focus on Pb-free packages to meet European Union mandated RoHS guidelines by 2006, with exemptions allowed for server and other networking hardware (1,2).Towards this goal, IBM has developed and qualified Pb-free and Pb-reduced packages that cover advanced semiconductor technologies such as 130nm and 90nm ground rules. In addition, for device performance reasons, the BEOL wiring layers on the high-performance 90nm or smaller ground rule devices also require low-k dielectric materials. Finally, due to tighter wiring ground rules and faster device performance requirements, the build-up laminate packages require thincore (400 um) and advanced wiring pitch in the build-up layers. IBM has partnered with Amkor Technology to qualify both 130nm and 90nm devices with Amkor developed Pb-free bumps using large die and build-up laminates, the details of which were presented at the 56th ECTC (3). The Sn-Ag Pbfree plated bumps were fabricated by Amkor on 300mm wafers with photosensitive polyimide (PSPI) passivation. Details of Amkor-Unitive plated Pb-free bump technology are discussed in Reference 4. The die size used was 14.7mm and the laminate qualified was 42.5mm with a structure of 4-2-4. We have extended the Pb-free low-k device technology to evaluate two additional elements: 65nm ground rules with enhanced low-k wiring layers on the die, and a 2-2-2 structure with thin core. The work reported here has been done with IBM silicon fabricated in the 300mm facility in East Fishkill, New York. Pb-free bumping and BA was carried out by Amkor.In this paper, we will summarize the Sn/Ag Pb-free plated bumps that have been qualified for low-k 65nm technology on thin-core build-up laminates. The bump pitch is 200um, and the laminate size is 42.5mm. One of the key issues addressed in this qualification was whether Pb-free bumps along with assembly to build-up laminates with thin-core result in enough stress to cause any low-k related fails such as delamination or cracks in the low-k wiring layers. In IBM this is carried out with special wiring and via-chains on the testdie that are monitored after assembly to package, and through reliability testing -perimeter lines, and delamination sensors, serpentines, and via-chains on the test-die that are tested for continuity and isolation of individual nets. These structures survive wafer-level stressing, and fails in modules are due to additional stress or damage induced by the bond and assembly processes. This is known as Chip-Package Interaction or CPI evaluation.Typical reliability stressing was carried out for Pb-free 65nm die for CPI and 2-2-2 PBGA package qualification described in the paper. The 200um pitch Pb-free bumps on a 216 sq.mm die successfully completed these reliability stresses for both CPI and package without any CPI net, bump or laminate wirin...

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Section: Introductionmentioning

confidence: 97%

Qualification of Low-k 65nm Technology Die with Pb-free Bumps on a 2-2-2 Laminate Package (PBGA) with Pb-free Assembly Processes

Ray

Muncy

McLaughlin

et al. 2007

2007 Proceedings 57th Electronic Components and Technology Conference

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“…For the high performance devices in the field of communication systems, high pin count package such as FC-BGA has been used to meet demands of high-speed signal transmission and high power characteristics. [1] And the COC structure, utilized chip-stacking technology, can miniaturize the device size generally. [2] For the demand of further high speed and wide band data transmission between LSI chips on SiP, the shorter transmission length of the COC interconnection with the high-count bumps would meet the future needs, and the COC-FCBGA, in the combination with the merit of the COC structure and FC-BGA, would be one of the best solutions.…”

Section: Introductionmentioning

confidence: 99%

Development of 30 micron Pitch Bump Interconnections for COC-FCBGA

Iwasaki

Watanabe

Baba

et al.

56th Electronic Components and Technology Conference 2006

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We developed the flip-chip bonding technology on ChipOn-Chip (COC) package with ultra-fine pitch bump, which leads advanced high performance devices. On this package, the realization of the metallographic behavior in the microbump interconnection is the substantial issue for achieving good bondability and reliability. In this paper, to implement Flip-Chip BGA package with COC structure (COC-FCBGA), the metal systems of micro-bump and the dimension especially metal plating thickness have been optimized by precise analysis. And it is confirmed that the specification we fixed on this package would meet sufficient quality level for fine pitch bonding. This COC-FCBGA technology will meet demands for high-end system solutions in very near future.

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“…Applying low-k ILD in devices adds the effect of resolving common signal delay problem because of its capabilities in lowering capacitance between signal lines. As die size reduces with device technology node, and its associated cost is realized, devices with low-k ILD are bound to increase [3,4]. Thus, the stacked die SiP which is gaining popularity, is bound inevitably use the devices with low-k ILD.…”

Section: Introductionmentioning

confidence: 99%