In the field of advanced electric devices using fine wafer process below the technology node of 130nm or 90nm, low dielectric constant inter-metal-dielectric (Low-k IMD) have been applied to have high speed operation. And from the environmental viewpoint on electric devices, elimination of the harmful materials like lead (Pb) material is one of the important activities. In such circumstances, we have developed Pb-free Flip-chip Ball Grid Array (FC-BGA) package for Low-k devices using organic substrate. From our experiments on 1296pin FC-BGA package with 12.4 x 12.4 mm size chip, it is concluded that applying solder bump composed of Sn-1.0Ag-0.5Cu and the low stress underfill with Tg 110 o C will realize the Pb-free FC-BGA on Low-k device.

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We developed the flip-chip bonding technology on ChipOn-Chip (COC) package with ultra-fine pitch bump, which leads advanced high performance devices. On this package, the realization of the metallographic behavior in the microbump interconnection is the substantial issue for achieving good bondability and reliability. In this paper, to implement Flip-Chip BGA package with COC structure (COC-FCBGA), the metal systems of micro-bump and the dimension especially metal plating thickness have been optimized by precise analysis. And it is confirmed that the specification we fixed on this package would meet sufficient quality level for fine pitch bonding. This COC-FCBGA technology will meet demands for high-end system solutions in very near future.

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