Realizing the benefits of structural test for Intel microprocessors

Mayberry, Mike; Johnson, Julian; Shahriari, Nahid; Tripp, M.

doi:10.1109/test.2002.1041795

Cited by 14 publications

(4 citation statements)

References 5 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Fig. 2 shows the relative breakdown of test time between different processor components for the Pentium 4 processor [26]. Cache testing consumes 53.3% of the total test time, and thereby represents the largest portion of the test flow.…”

Section: Industrial Cache Testingmentioning

confidence: 99%

“…These memories are organized in multiple layers [e.g., level-1 (L1), level-2 (L2), and level-3 (L3) caches], with different performance requirements, and are designed to serve various system requirements (e.g., instruction caches versus data caches) [23]. The amount of on-chip memory embedded alongside the processor occupies about 50% of the chip area [26], and is expected to reach 90% by 2011 [8]. In terms of transistor count, the numbers are even more staggering.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Test Set Development for Cache Memory in Modern Microprocessors

Al-Ars

Hamdioui

Gaydadjiev

et al. 2008

IEEE Trans. VLSI Syst.

View full text Add to dashboard Cite

Abstract-Up to 53% of the time spent on testing current Intel microprocessors is needed to test on-chip caches, due to the high complexity of memory tests and to the large amount of transistors dedicated to such memories. This paper discusses the methodology used to develop effective and efficient cache tests, and the way it is implemented to optimize the test set used at Intel to test their 512-kB caches manufactured in a 0.13-m technology. An example is shown where a maximal test set of 15 tests with a corresponding maximum test time of 160.942 ms/chip is optimized to only six tests that require a test time of only 30.498 ms/chip.

show abstract

Section: Industrial Cache Testingmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Test Set Development for Cache Memory in Modern Microprocessors

Al-Ars

Hamdioui

Gaydadjiev

et al. 2008

IEEE Trans. VLSI Syst.

View full text Add to dashboard Cite

show abstract

“…SBST techniques have also been integrated into manufacturing test processes of some chip manufacturers. Intel has been using a combination of structural and functional test methods for testing of processors in the last decade [8, 9].…”

Section: Introductionmentioning

confidence: 99%

HASTI: hardware‐assisted functional testing of embedded processors in idle times

Kamran

2019

IET Computers & Digital Techniques

View full text Add to dashboard Cite

In the past decades, software-based self-testing (SBST) which is testing of a processing core using its native instructions has attracted much attention. However, efficient SBST of a processing core which is deeply embedded in a multicore architecture is still an open issue. In this study, inspiring from built-in self-test methods, the authors place several number of hardware test components next to the processing cores in order to overcome existing SBST challenges. These test components facilitate quick testing of embedded cores by providing several mechanisms such as virtual fetch, virtual jump, fake load & store, and segmented test application. In order to enable segmented test application, they propose the concept of test snippet and a test snippet generation approach. The result is the capability of testing embedded cores in short idle times leading to efficient online testing of the cores with zero performance overhead. The authors' results show that their test snippet generation approach not only leads to the production of test snippets which are properly fitted the proposed test architecture but also its final fault coverage is comparable and even a little better than the fault coverage of the best existing methods.

show abstract

“…The IEEE 1149.1 standard boundary scan technique and full scan technique are applied broadly in the test of the large-scale integrated circuit such as microprocessor, digital signal processor etc [1] , [2] . Our designed motor control digital signal processor, for linking with system operation platform, establishes scan mechanism which can real-time access all registers and can supervise and control the procedure which run into MCDSP, can provide breaking point simulation, single step debug of procedure, becoming a testability architecture which can scan, test, and operated with system platform.…”

Section: Introductionmentioning

confidence: 99%

Testability design of motor control digital signal processor

Yan

2010

2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology

View full text Add to dashboard Cite

According to architecture characteristics of the motor control digital signal processor (MCDSP), we select standard boundary scan test which is compatible with IEEE 1149.1 as main method, and full scan test as complementary method to test whole chip. Adopted self-definition address registers, data registers, control registers together, boundary scan test makes the use of the original core circuit of MCDSP, and uses MARCH B algorithm to test RAM, ROM and registers stacks, reducing the hardware expense; full scan technique establishes a single scan chain which has function of multi-chains, reducing test application time. Compared to traditional test methods, the combined methods come to a good equilibrium between hardware expense and test application time.

show abstract

Realizing the benefits of structural test for Intel microprocessors

Cited by 14 publications

References 5 publications

Test Set Development for Cache Memory in Modern Microprocessors

Test Set Development for Cache Memory in Modern Microprocessors

HASTI: hardware‐assisted functional testing of embedded processors in idle times

Testability design of motor control digital signal processor

Contact Info

Product

Resources

About