Recent Progress and Challenges Regarding Carbon Nanotube On-Chip Interconnects

Abstract

Along with deep scaling transistors and complex electronics information exchange networks, very-large-scale-integrated (VLSI) circuits require high performance and ultra-low power consumption. In order to meet the demand of data-abundant workloads and their energy efficiency, improving only the transistor performance would not be sufficient. Super high-speed microprocessors are useless if the capacity of the data lines is not increased accordingly. Meanwhile, traditional on-chip copper interconnects reach their physical limitation of resistivity and reliability and may no longer be able to keep pace with a processor’s data throughput. As one of the potential alternatives, carbon nanotubes (CNTs) have attracted important attention to become the future emerging on-chip interconnects with possible explorations of new development directions. In this paper, we focus on the electrical, thermal, and process compatibility issues of current on-chip interconnects. We review the advantages, recent developments, and dilemmas of CNT-based interconnects from the perspective of different interconnect lengths and through-silicon-via (TSV) applications.

Direct Application of Carbon Nanotubes (CNTs) Grown by Chemical Vapor Deposition (CVD) for Integrated Circuits (ICs) Interconnection: Challenges and Developments

“…However, as manufacturing technology continues to advance and IC dimensions continue to shrink, the size of interconnections also needs to be reduced accordingly, and copper-based interconnects are increasingly exposed to drawbacks. For example, the increase in resistance and capacitance [2], thermal effects [3], and electromigration (EM) [4]. The most direct and effective way to solve the above problems is to find a new conductive material to replace copper.…”

Electrochemically reduced graphene oxide (ERGO)-Cu bilayer structure fabricated at room temperature for future interconnects

“…2,3 Therefore, graphene-based materials show great potential for future interconnect, such as composite made of copper and graphene, 4 graphene-Cu bilayer structure, 5 and pure graphene interconnect. 6 In these structures, graphene-Cu bilayer has been proposed to be highly conductive and therefore has an extensive interconnect application. 8 Few-layers graphene can be deposited on the upper layer of the copper by chemical vapour deposition (CVD) to form a graphene-Cu bilayer interconnect structure.…”

“…2,3 Therefore, graphene-based materials show great potential for future interconnect, such as composite made of copper and graphene, 4 graphene-Cu bilayer structure, 5 and pure graphene interconnect. 6…”

Thermodynamic Multi-Field Coupling Optimization of Microsystem Based on Artificial Intelligence

“…Excessive thermal stress will bring serious thermal stress problems to the complex three-dimensional integrated structure, causing TSV copper pillars to peel off the contact surface of the substrate, or cracks in the bonding, micro bumps, and sink bottom [ 8 ]. Even if there is no destruction to device structure, the reduction of device carrier mobility caused by thermal stress will also lead to the deterioration of circuit performance [ 9 , 10 ]. Therefore, reducing the thermal stress in the silicon substrate is particularly important to ensure the reliability of the device.…”