Reconfigurable Digital Front-End Hardware for Wireless Base-Station Transmitters: Analysis, Design and FPGA Implementation

Lashkarian, N.; Hemphill, E.; Tarn, H.; Parekh, H.; Dick, Chris

doi:10.1109/tcsi.2007.902608

Cited by 10 publications

(4 citation statements)

References 10 publications

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“…Hence, at the output of the left and right data path, there would be uneven number of relatively insignificant bits available. But in this paper, it is needed to have even number of locations free so that the video bits can be incorporated and reconfigurability [11,8] can be applied. Hence the control word is changed to have even number of 1's and 0's which in turn demands that the whole structure be changed.…”

Section: Proposed Modified Enhanced Merge Sorter Networkmentioning

confidence: 99%

“…They can essentially perform the four operations required for each bit in two instructions (EXTRACT, DEPOSIT), resulting in 2n instructions for any arbitrary permutation of n bits. Pre-defined permutations with some regular patterns can of course be done in fewer instructions, for example, the permutations in DES [8]. But, in general, an arbitrary 64-bit permutation could take 128 or 256 instructions on current microprocessors.…”

Section: Introductionmentioning

confidence: 99%

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FPGA-based Low Power Audio Subword Sorter Unit

Karthigaikumar¹,

Baskaran²

2009

IETE J Res

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The security of audio data in high end communication applications like satellites and radars is an issue of concern these days. Designing a processor at the chip level for this requirement is by itself a challenge to VLSI engineers. This paper aims to design a HDL based novel audio subword sorter unit, which is less complex in structure and highly efficient in terms of security. In this paper, we examine the hardware implementation of powerful permutation instruction group (GRP) with low power. This is done at the integrated chip (IC-level) using Verilog HDL and can be implemented in FPGA. To our knowledge this is the first audio subword sorter unit implemented in FPGA.

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Section: Proposed Modified Enhanced Merge Sorter Networkmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

FPGA-based Low Power Audio Subword Sorter Unit

Karthigaikumar¹,

Baskaran²

2009

IETE J Res

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“…To reduce the BS costs and to facilitate the migration to LTE, multi-band multi-standard BSs (incl. the case of Remote Radio Head (RRH) deployment) are desired (see [1][2][3] etc.). Such BSs are expected to be very flexible and efficient.…”

Section: Introductionmentioning

confidence: 99%

Smart RF signal processing for advanced transmitters: From theory to practice

Luo

Liszewski

Schubert

et al. 2012

2012 International Symposium on Signals, Systems, and Electronics (ISSSE)

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Multi-band multi-standard Base Stations (BS) are believed to be one promising solution to manage the coexistence of different technological standards (e.g. 2G/3G/4G) with reasonable installation and operation costs. Except for multi-technology baseband (BB) units and multi-band/broadband RF-frontends e.g. antenna and Power Amplifier (PA), the realization of such BSs requires sophisticated cooperation between digital BB and analog components to reduce frontend costs and to enhance energy efficiency, flexibility and transmission quality. Such a concept is called "Smart RF". In this paper, we investigate the prototype implementation of practical digital signal processing techniques for performance enhancement of the RF-frontends and analog BB components in multi-band multi-standard transmitters. These techniques include the digital compensations of I/Q-imbalance, modulator (MOD) DC-offset and PA nonlinearity. A prototype platform is described where realtime impairment compensation circuits are implemented. Practical implementation issues incl. complexity and synchronization are discussed. Finally, experimental measurements are presented, which verify the effectiveness of the implemented Smart RF techniques.

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“…The channelizer extracts multiple narrowband channels (frequency bands) from a wideband signal. Low complexity, high-speed and reconfigurable channelizers are required in the SDR receivers [2].…”

Section: Introductionmentioning

confidence: 99%

An Area-efficient Non-uniform Filter Bank for Low Overhead Reconfiguration of Multi-standard Software Radio Channelizers

Mahesh

Vinod

2010

J Sign Process Syst

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The channelizer in a software defined radio (SDR) base station extracts individual radio channels from the digitized wideband input signal at a very high sampling rate. The base station channelizer must be able to simultaneously extract multiple channels of non-uniform bandwidths corresponding to channel bandwidths of different communication standards. Reconfigurability and low complexity are the two key requirements in the SDR channelizer. A new reconfigurable filter bank (FB) architecture based on interpolation and masking technique for SDR channelizers is proposed in this paper. The proposed FB can be used for obtaining very narrow passband channels with extremely low complexity. Using a cascaded structure of the proposed FB, it is possible to extract channels of fractional passband widths by changing the interpolation factor. Design example shows that the proposed FB offers complexity reduction of 84% over the conventional per-channel (PC) approach. The proposed FB has been implemented and tested on Xilinx Virtex 2v3000ff1152-4 FPGA. Implementation results show that the proposed FB offers area reduction of 48.37%, speed improvement of 52.7% and power reduction of 75.9% over the PC approach.

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Reconfigurable Digital Front-End Hardware for Wireless Base-Station Transmitters: Analysis, Design and FPGA Implementation

Cited by 10 publications

References 10 publications

FPGA-based Low Power Audio Subword Sorter Unit

FPGA-based Low Power Audio Subword Sorter Unit

Smart RF signal processing for advanced transmitters: From theory to practice

An Area-efficient Non-uniform Filter Bank for Low Overhead Reconfiguration of Multi-standard Software Radio Channelizers

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