Reconfigurable hardware architecture for Mean Level and log-t CFAR detectors in FPGA implementations

Jiafei, Zhao; Jiang, Rongkun; Yang, Hao; Wang, Xuetian

doi:10.1587/elex.16.20190584

Cited by 5 publications

(3 citation statements)

References 29 publications

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“…Table 4 shows a comparison of the results between the proposed method and other CFAR processors in [ 22 , 23 , 24 , 25 , 26 , 27 , 28 , 29 , 30 , 31 ]. For a fair comparison, we compared the speed performance in terms of the normalized operation time,

, which was calculated based on FPGA process technology [ 32 ].…”

Section: Hardware Architecturementioning

confidence: 99%

“…The CFAR processor in [ 29 ] has the advantages of low hardware complexity and fast operation time but requires prior information to generate thresholds. A CFAR processor that can be applied to Rayleigh distribution and no-Rayleigh distribution by applying mean level CFAR and log-t CFAR was presented [ 30 ]. However, it has disadvantages in terms of high hardware complexity and long operation time.…”

Section: Hardware Architecturementioning

confidence: 99%

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FPGA Implementation of Efficient CFAR Algorithm for Radar Systems

Sim

Heo

Jung

et al. 2023

Sensors

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The constant false-alarm rate (CFAR) algorithm is essential for detecting targets during radar signal processing. It has been improved to accurately detect targets, especially in nonhomogeneous environments, such as multitarget or clutter edge environments. For example, there are sort-based and variable index-based algorithms. However, these algorithms require large amounts of computation, making them difficult to apply in radar applications that require real-time target detection. We propose a new CFAR algorithm that determines the environment of a received signal through a new decision criterion and applies the optimal CFAR algorithms such as the modified variable index (MVI) and automatic censored cell averaging-based ordered data variability (ACCA-ODV). The Monte Carlo simulation results of the proposed CFAR algorithm showed a high detection probability of 93.8% in homogeneous and nonhomogeneous environments based on an SNR of 25 dB. In addition, this paper presents the hardware design, field-programmable gate array (FPGA)-based implementation, and verification results for the practical application of the proposed algorithm. We reduced the hardware complexity by time-sharing sum and square operations and by replacing division operations with multiplication operations when calculating decision parameters. We also developed a low-complexity and high-speed sorter architecture that performs sorting for the partial data in leading and lagging windows. As a result, the implementation used 8260 LUTs and 3823 registers and took 0.6 μs to operate. Compared with the previously proposed FPGA implementation results, it is confirmed that the complexity and operation speed of the proposed CFAR processor are very suitable for real-time implementation.

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, which was calculated based on FPGA process technology [ 32 ].…”

Section: Hardware Architecturementioning

confidence: 99%

Section: Hardware Architecturementioning

confidence: 99%

FPGA Implementation of Efficient CFAR Algorithm for Radar Systems

Sim

Heo

Jung

et al. 2023

Sensors

View full text Add to dashboard Cite

show abstract

“…Detecting targets is the fundamental task of a radar system. As an effective method for target detection, the constant false alarm rate (CFAR) technology can maximize the detection probability while maintaining a constant false alarm probability [6,7]. In previous studies, several types of CFAR processors have been proposed based on the mechanism of a sliding reference window.…”

Section: Introductionmentioning

confidence: 99%

Robust CFAR Detection for Multiple Targets in K-Distributed Sea Clutter Based on Machine Learning

2019

Self Cite

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For K-distributed sea clutter, a constant false alarm rate (CFAR) is crucial as a desired property for automatic target detection in an unknown and non-stationary background. In multiple-target scenarios, the target masking effect reduces the detection performance of CFAR detectors evidently. A machine learning based processor, associating the artificial neural network (ANN) and a clustering algorithm of density-based spatial clustering of applications with noise (DBSCAN), namely, DBSCAN-CFAR, is proposed herein to address this issue. ANN is trained with a symmetrical structure to estimate the shape parameter of background clutter, whereas DBSCAN is devoted to excluding interference targets and sea spikes as outliers in the leading and lagging windows that are symmetrical about the cell under test (CUT). Simulation results verified that the ANN-based method provides the optimal parameter estimation results in the range of 0.1 to 30, which facilitates the control of actual false alarm probability. The effectiveness and robustness of DBSCAN-CFAR are also confirmed by the comparisons of conventional CFAR processors in different clutter conditions, comprised of varying target numbers, shape parameters, and false alarm probabilities. Although the proposed ANN-based DBSCAN-CFAR processor incurs more elapsed time, it achieves superior CFAR performance without a prior knowledge on the number and distribution of interference targets.

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An improved CFAR algorithm for multiple environmental conditions

Rihan,

Nossair,

Mubarak

2024

SIViP

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The primary objective of radar digital signal processing is to detect and identify targets in complicated situations, such as those involving clutter or several closely positioned targets. The constant false alarm rate (CFAR) method is more effective for target recognition and has better control over the false alarm rate. Many studies have been conducted on the design of CFAR, but previous CFAR algorithms have not been effective in all or most environmental fields and target scenarios. In this study, an algorithm called Censored Mean Clutter Map CFAR (CM-CM CFAR) has been developed and tested for various environmental conditions. When compared to a fixed false alarm rate, the suggested CFAR algorithm’s Monte Carlo simulation results demonstrated a high detection probability in a variety of environments. This work designs a real-time CM-CM CFAR processor using field-programmable gate array (FPGA) technologies. Xilinx ARTIX 7 FPGA technology is used to develop and map a scalable parallel framework. Consequently, the implementation required 23,741 LUTs and 1825 FF. It is verified that the complexity and operating speed of the suggested CFAR processor are extremely appropriate for real-time implementation when compared to the results of the previously proposed FPGA implementation.

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Reconfigurable hardware architecture for Mean Level and log-t CFAR detectors in FPGA implementations

Cited by 5 publications

References 29 publications

FPGA Implementation of Efficient CFAR Algorithm for Radar Systems

FPGA Implementation of Efficient CFAR Algorithm for Radar Systems

Robust CFAR Detection for Multiple Targets in K-Distributed Sea Clutter Based on Machine Learning

An improved CFAR algorithm for multiple environmental conditions

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