Reconfigurable memory based AES co-processor

Chaves, Ricardo; Kuzmanov,; Vassiliadis,; Sousa, Leonel

doi:10.1109/ipdps.2006.1639441

Cited by 47 publications

(36 citation statements)

References 8 publications

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“…The implementation was modified to use the new interfaces used to access memory, causing an additional 2 cycles to be needed for reading and writing data in the case of the memory hierarchy with queues, and an additional 8 for the basic memory hierarchy, and the hierarchy with cache. This results in a lower theoretical maximum throughput compared to the implementation described in [25].…”

Section: Aesmentioning

confidence: 95%

“…The application used to test our system is an Advanced Encryption Standard (AES) cryptography application proposed in [25]. AES is a symmetric-key encryption algorithm, which means that the same key is used both for encryption and decryption.…”

Section: Aesmentioning

confidence: 99%

“…We used an implementation of the approach described in [25]. In this implementation the shift rows and mix columns steps are combined into a single table lookup.…”

Section: Aesmentioning

confidence: 99%

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General Purpose Computing with Reconfigurable Acceleration

Brandon

Sourdis

Gaydadjiev

2010

2010 International Conference on Field Programmable Logic and Applications

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In this thesis we describe a new generic approach for accelerating software functions using a reconfigurable device connected through a high-speed link to a general purpose system. In order for our solution to be generic, as opposed to related ISA extension approaches, we insert system calls into the original program to control the reconfigurable accelerator using a compiler plug-in. We define specific mechanisms for the communication between the reconfigurable device, the host general purpose processor and the main memory. The reconfigurable device is controlled by the host through system calls provided by the device driver, and initiates communication by raising interrupts; it further has direct accesses to the main memory (DMA) operating in the virtual address space. To do so, the reconfigurable device supports address translation, while the driver serves the device interrupts, ensures that shared data in the host-cache remain coherent, and handles memory protection and paging. The system is implemented using a machine which provides a HyperTransport bus connecting a Xilinx Virtex4-100 FPGA to the host. We evaluate alternative design choices of our proposal using an AES application and accelerating its most computationally intensive function. Our experimental results show that our solution is up to 5× faster than software and achieves a processing throughput equal to the theoretical maximum. n this thesis we describe a new generic approach for accelerating software functions using a reconfigurable device connected through a high-speed link to a general purpose system. In order for our solution to be generic, as opposed to related ISA extension approaches, we insert system calls into the original program to control the reconfigurable accelerator using a compiler plug-in. We define specific mechanisms for the communication between the reconfigurable device, the host general purpose processor and the main memory. The reconfigurable device is controlled by the host through system calls provided by the device driver, and initiates communication by raising interrupts; it further has direct accesses to the main memory (DMA) operating in the virtual address space. To do so, the reconfigurable device supports address translation, while the driver serves the device interrupts, ensures that shared data in the host-cache remain coherent, and handles memory protection and paging. The system is implemented using a machine which provides a HyperTransport bus connecting a Xilinx Virtex4-100 FPGA to the host. We evaluate alternative design choices of our proposal using an AES application and accelerating its most computationally intensive function. Our experimental results show that our solution is up to 5× faster than software and achieves a processing throughput equal to the theoretical maximum. Laboratory: Computer Engineering Codenumber : CE-MS

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Section: Aesmentioning

confidence: 95%

Section: Aesmentioning

confidence: 99%

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General Purpose Computing with Reconfigurable Acceleration

Brandon

Sourdis

Gaydadjiev

2010

2010 International Conference on Field Programmable Logic and Applications

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“…Examples of AES implementations for stand-alone FPGAs are [7][8][9][10][11], providing 2-30 GBit/sec throughputs. Hybrid solutions, coupling a processor with FPGA technology, are implemented in the Xilinx Virtex II Pro platform [8,12], achieving performance up to 1.2 GBit/sec. For embedded applications, where the area budget is a constraints, devices with restricted size are proposed.…”

Section: Related Workmentioning

confidence: 99%

Implementation of AES/Rijndael on a dynamically reconfigurable architecture

Mucci

Vanzolini

Lodi

et al. 2007

2007 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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“…Following them in 2004 Rouvroy et al [2] used a similar concept and achieved better results utilizing 163 slices and 3 BRAMs. Chaves et al [3] demonstrates an efficient use of BRAMs in a reconfigurable memory based co-processor. In [4] Chang et al explain the use of BRAMs to save on area and implements an AES with 8 bit datapath using only 130 slices and 4 BRAMs.…”

Section: Introductionmentioning

confidence: 99%

Investigation of DPA Resistance of Block RAMs in Cryptographic Implementations on FPGAs

Shah¹,

Velegalati

Kaps

et al. 2010

2010 International Conference on Reconfigurable Computing and FPGAs

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Abstract-Security at low cost is an important factor for cryptographic hardware implementations. Unfortunately, the security of cryptographic implementations is threatened by Side Channel Analysis (SCA). SCA attempts to discover the secret key of a device by exploiting implementation characteristics and bypassing the algorithm's mathematical security. Differential Power Analysis (DPA) is a type of SCA, which exploits the device's power consumption characteristics. Several countermeasures to DPA have been proposed, however, all of them increase security at the cost of increased area which in-turn leads to increased power consumption and reduced throughput. FPGAs are popular due to their reconfigurability, lower development cost, off-the-shelf availability and shorter time to market. Block RAMs (BRAM) are large memories in FPGAs that are commonly used as ROM, FIFO, Look-up tables, etc. In this paper we explore the DPA resistance of BRAMs in Xilinx FPGAs and verify if their usage can improve the security. The results of our Advanced Encryption Standard (AES) implementations show that using BRAMs alone can improve the security over a look-up table (LUT) only design 9 times. Applying Separated Dynamic Differential Logic (SDDL) for FPGAs, a countermeasure against DPA, to this design doubles the security again leading to an 18 fold increase over the unprotected LUT design.

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Reconfigurable memory based AES co-processor

Cited by 47 publications

References 8 publications

General Purpose Computing with Reconfigurable Acceleration

General Purpose Computing with Reconfigurable Acceleration

Implementation of AES/Rijndael on a dynamically reconfigurable architecture

Investigation of DPA Resistance of Block RAMs in Cryptographic Implementations on FPGAs

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