Reconfigurable Radix-2<sup>k</sup>×3 Feedforward FFT Architectures

Tsai, Wei‐Lun; Chen, Sau-Gee; Huang, Shen-Jui

doi:10.1109/iscas.2019.8702346

Cited by 5 publications

(9 citation statements)

References 15 publications

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“…[ACC + 21] and [CHK + 21] introduce various NTT extension algorithms by applying versatile FFT tricks, enabling the software implementation of polynomial multiplication on NTT unfriendly rings. In terms of architecture level design, unlike the popular pipelined FFT architecture, such as single delay feedback (SDF) and multiple delay commutator (MDC) [TCH19] [HT96], the current NTT core mainly adopts memory-based architecture allowing for a trade-off between area and performance. [CMV + 15] proposes a high-speed pipelined polynomial multiplication architecture based on constant geometry radix-2 NTT.…”

Section: Related Workmentioning

confidence: 99%

CFNTT: Scalable Radix-2/4 NTT Multiplication Architecture with an Efficient Conflict-free Memory Mapping Scheme

Chen

Yang

Yin

et al. 2021

TCHES

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Number theoretic transform (NTT) is widely utilized to speed up polynomial multiplication, which is the critical computation bottleneck in a lot of cryptographic algorithms like lattice-based post-quantum cryptography (PQC) and homomorphic encryption (HE). One of the tendency for NTT hardware architecture is to support diverse security parameters and meet resource constraints on different computing platforms. Thus flexibility and Area-Time Product (ATP) become two crucial metrics in NTT hardware design. The flexibility of NTT in terms of different vector sizes and moduli can be obtained directly. Whereas the varying strides in memory access of in-place NTT render the design for different radix and number of parallel butterfly units a tough problem. This paper proposes an efficient conflict-free memory mapping scheme that supports the configuration for both multiple parallel butterfly units and arbitrary radix of NTT. Compared to other approaches, this scheme owns broader applicability and facilitates the parallelization of non-radix-2 NTT hardware design. Based on this scheme, we propose a scalable radix-2 and radix-4 NTT multiplication architecture by algorithm-hardware co-design. A dedicated schedule method is leveraged to reduce the number of modular additions/subtractions and modular multiplications in radix-4 butterfly unit by 20% and 33%, respectively. To avoid the bit-reversed cost and save memory footprint in arbitrary radix NTT/INTT, we put forward a general method by rearranging the loop structure and reusing the twiddle factors. The hardware-level optimization is achieved by excavating the symmetric operators in radix-4 butterfly unit, which saves almost 50% hardware resources compared to a straightforward implementation. Through experimental results and theoretical analysis, we point out that the radix-4 NTT with the same number of parallel butterfly units outperforms the radix-2 NTT in terms of area-time performance in the interleaved memory system. This advantage is enlarged when increasing the number of parallel butterfly units. For example, when processing 1024 14-bit points NTT with 8 parallel butterfly units, the ATP of LUT/FF/DSP/BRAM n radix-4 NTT core is approximately 2.2 × /1.2 × /1.1 × /1.9 × less than that of the radix-2 NTT core on a similar FPGA platform.

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Section: Related Workmentioning

confidence: 99%

CFNTT: Scalable Radix-2/4 NTT Multiplication Architecture with an Efficient Conflict-free Memory Mapping Scheme

Chen

Yang

Yin

et al. 2021

TCHES

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“…(Chu Yu and mao-Hsu Yen 2015; W. Tsai et al 2019) utilizes the properties of twiddle factors and constant multiplication techniques to meet the low area and power requirements. The complex multiplication involving four multiplications is reduced to three multiplications has been reported in the past literature.…”

Section: Background and Related Workmentioning

confidence: 99%

Low Power Complex Multiplication using Pre-computation Technique For FFT Algorithm in Wearable ECG Gadgets

Joshi¹

2020

Biosci. Biotech. Res. Comm

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The focus on wearable devices for biomedical applications is gaining a lot of research and market interest. Heart diseases remain by far the main cause of death and a challenging problem for biomedical engineers to monitor and analyze. Electrocardiography (ECG) is an essential practice in heart medicine. However, wearable ECG gadgets for real time analysis still faces computational challenges, especially when multiple lead signals are to be analyzed in parallel, in real time, and under increasing sampling frequencies and battery operated gadgets. Another challenge is the computation of Fast Fourier Transform (FFT) on huge amounts of data that may grow to days of recordings. In this research we present the comparative study of FFT calculation best suitable for power optimized applications in the biomedical field and exclusive performance enhancement by reducing dynamic power consumption. ECG application specific to FFT calculation to the final hardware-software( HW/SW) architecture is the focus of this paper.

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“…Nowadays, pipelined FFT hardware architectures for NP2 sizes mostly consider single-path delay feedback (SDF) architectures [18], [19], [20], [21], [22], [23], [24], [25], [26], with the exception of [27]. However, for NP2 sizes, SDF architectures are not as efficient as could be expected: Although SDF architectures process data in series at a rate of one sample per clock cycle, the butterflies that they use operate data in parallel.…”

mentioning

confidence: 99%

“…In order to achieve this, a feasible approach is to develop serial butterflies with one input and one output that process one sample per clock cycle, instead of processing several samples per clock cycle in parallel. With this aim, previous works have been proposed in [26], [27], and [28]. In [26], a novel design for a radix-3 SDF butterfly is presented.…”

mentioning

confidence: 99%

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Serial Butterflies for Non-Power-of-Two FFT Architectures in 5G and Beyond

Bautista

Garrido

López‐Vallejo

2023

IEEE Trans. Circuits Syst. I

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This paper presents new serial butterflies for nonpower-of-two (NP2) fast Fourier transform (FFT) architectures. The paper considers radices 2, 3, 4, and 5, which are used in FFTs for 5G systems. Current designs for non-power-of-two FFTs are mostly based on the single-path delay feedback (SDF) architecture. This type of architecture processes data arriving in series. However, it uses butterflies with several parallel inputs. This results in low utilization, as the butterflies have to wait for all the inputs before they start to process them. Conversely, the proposed approach allows to calculate the butterflies on data that arrive in series. This removes waiting times and reduces the number of hardware components such as multipliers and adders. As a result, the proposed butterflies achieve high performance and provide a significant reduction in area and power consumption with respect to parallel butterflies. Thus, they are an efficient solution when data must be processed in series in the butterflies.

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Reconfigurable Radix-2^k×3 Feedforward FFT Architectures

Cited by 5 publications

References 15 publications

CFNTT: Scalable Radix-2/4 NTT Multiplication Architecture with an Efficient Conflict-free Memory Mapping Scheme

CFNTT: Scalable Radix-2/4 NTT Multiplication Architecture with an Efficient Conflict-free Memory Mapping Scheme

Low Power Complex Multiplication using Pre-computation Technique For FFT Algorithm in Wearable ECG Gadgets

Serial Butterflies for Non-Power-of-Two FFT Architectures in 5G and Beyond

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Reconfigurable Radix-2k×3 Feedforward FFT Architectures

Cited by 5 publications

References 15 publications

CFNTT: Scalable Radix-2/4 NTT Multiplication Architecture with an Efficient Conflict-free Memory Mapping Scheme

CFNTT: Scalable Radix-2/4 NTT Multiplication Architecture with an Efficient Conflict-free Memory Mapping Scheme

Low Power Complex Multiplication using Pre-computation Technique For FFT Algorithm in Wearable ECG Gadgets

Serial Butterflies for Non-Power-of-Two FFT Architectures in 5G and Beyond

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Reconfigurable Radix-2^k×3 Feedforward FFT Architectures