Reduced Instrumentation and Optimized Fault Injection Control for Dependability Analysis

Vanhauwaert, Pierre; Leveugle, Régis; Roché, Philippe

doi:10.1109/vlsisoc.2006.313220

Cited by 15 publications

(8 citation statements)

References 10 publications

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“…Therefore, the major drawback of using simulation techniques is the time consuming effort resulting from the huge computational power required to perform circuit simulation under a large number of faulty conditions. Emulation-based fault injection techniques have been proposed in past years with the objective of accelerating fault injections campaigns [16][17][18][19]. Features present in FPGAs like reconfiguration and readback capabilities are used to increase the observability and controllability of a circuit under test (CUT), making FPGAs important tools for fault injection emulation.…”

Section: Validation Via Fault Injectionmentioning

confidence: 99%

Non-intrusive fault tolerance in soft processors through circuit duplication

Ferlini

Silva

Bezerra

et al. 2012

2012 13th Latin American Test Workshop (LATW)

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The flexibility introduced by Conunercial-Off-The Shelf (COTS) SRAM based FPGAs in on-board system designs make them an attractive option for military and aerospace applications. However, the advances towards the nanometer technology come together with a higher vulnerability of integrated circuits to radiation perturbations. In mission critical applications it is important to improve the reliability of applications by using fault-tolerance techniques. In this work, a non-intrusive fault tolerance technique has been developed. The proposed technique targets soft processors (e.g. LEON3), and its detection mechanism uses a Bus Monitor to compare output data of a main soft-processor with its redundant module. In case of a mismatch, an error signal is activated, triggering the proposed fault tolerance strategy. This approach shows to be more efficient than the state-of-the-art Triple Modular Redundancy (TMR) and Software Implemented Hardware Fault Tolerance (SIHFT) approaches in order to detect and to correct faults on the fly with low area overhead and with no major performance penalties. The chosen case study is an under development On Board Computer (OBC) system, conceived to be employed in future missions of the Brazilian Institute of Space Research (INPE).

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Section: Validation Via Fault Injectionmentioning

confidence: 99%

Non-intrusive fault tolerance in soft processors through circuit duplication

Ferlini

Silva

Bezerra

et al. 2012

2012 13th Latin American Test Workshop (LATW)

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“…As all the Flip-Flops (FFs) that constitute the pipeline registers are chip-enabled it is necessary to control both their data input and their chipenable input. As a consequence we have extended the solution proposed in [5]. For each targeted FF, it consists in inserting extra logic so as to invert the value memorized.…”

Section: A General Descriptionmentioning

confidence: 99%

“…in which FF the fault has to be injected) and to load these data in parallel. The injection controller is further detailed in [5]. For our experiments the board used is a Xilinx ML310 and the embedded processor is a hard processor core, the PowerPC core embedded in the Virtex2Pro FPGA.…”

Section: A General Descriptionmentioning

confidence: 99%

Usefulness and effectiveness of HW and SW protection mechanisms in a processor-based system

Vanhauwaert¹,

Portolan²,

Leveugle³

et al. 2008

2008 15th IEEE International Conference on Electronics, Circuits and Systems

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Fault-injection based dependability analysis has proved to be an efficient mean to predict the behavior of a circuit in presence of faults. Emulation-based approaches enable fast and flexible analyses of significant designs such as processors running significant application software. This paper presents the results obtained with an encryption application and questions the usefulness and the effectiveness of detection mechanisms in both hardware and software.

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“…the circuit is instrumented. The instrumentation is performed on the netlist generated by the synthesis of the RT-Ievel description, using an extension of the solution described in [12] that also allows us to inject bit-flips in flip-flops (FFs) with an Enable signal [13].…”

mentioning

confidence: 99%

“…in which FF the fault has to be injected) and to load these data in parallel. The injection controller is further detailed in [12]. For our experiments the board used is a Xilinx MUIO and the embedded processor is a hard processor core, the PowerPC core embedded in the Virtex2Pro FPGA.…”

mentioning

confidence: 99%

Efficiency of probabilistic testability analysis for soft error effect analysis: A case study

Vanhauwaert

Leveugle

2009

2009 4th International Conference on Design &Amp; Technology of Integrated Systems in Nanoscal Era

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Evaluating the potential functional effects ofsoft errors (single or multiple bit-jlips) in digital circuits becomes a critical design constraint. The usual approaches, based on fault injection techniques, suffer several limitations. New approaches, better suited to large circuits with complex workloads, are therefore suitable. An innovative approach was recently proposed, based on probabilistic testability analysis. This paper compares the presented results with results obtainedfrom extensive fault injection campaigns.

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Reduced Instrumentation and Optimized Fault Injection Control for Dependability Analysis

Cited by 15 publications

References 10 publications

Non-intrusive fault tolerance in soft processors through circuit duplication

Non-intrusive fault tolerance in soft processors through circuit duplication

Usefulness and effectiveness of HW and SW protection mechanisms in a processor-based system

Efficiency of probabilistic testability analysis for soft error effect analysis: A case study

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