Reduced Mechanical Strain in Bendable a-IGZO TFTs Under Dual-Gate Driving

Excellent Mechanical Durability of In‐Folding Stress of Poly‐Si Thin‐Film Transistor on Plastic Substrate Compared with Out‐Folding: Generation of Gate Leakage Currents in Flexible Poly‐Si Thin‐Film Transistor by Out‐Folding and Bias‐Temperature Stress

“…The "k" is the fitting constant and was found to be smaller for the in-folding (k ¼ 0.06) than that of out-folding (k ¼ 0.08), and both k values were found to be smaller than the reported oxide semiconductor TFTs. [36] Gleskova et al reported mechanical strain-induced failure analysis such as crack formation in silicon TFTs. [37] They explained that tensile strain-induced electrical degradation occurs mainly due to elastically deforming until crack formation.…”

Robust Oxide Thin-Film Transistors With Embedded CNT Buried Layer for Stretchable Electronics

“…9(c)-(d), we performed TCAD simulation to check the role of CNT layer inside PI layers once external mechanical strain is incident on flexible a-IGZO TFTs. We created bendable structures with single CNT and CNT+GO with CNT buried layers while considering an arbitrary bending radius (R) using Devedit device simulator of Silvaco TCAD [24]. For mechanical strain (ε) distribution, we performed victory 3D stress distribution module and the mechanical properties of different TFT and substrate layers are listed in TABLE 1 [24].…”

“…We created bendable structures with single CNT and CNT+GO with CNT buried layers while considering an arbitrary bending radius (R) using Devedit device simulator of Silvaco TCAD [24]. For mechanical strain (ε) distribution, we performed victory 3D stress distribution module and the mechanical properties of different TFT and substrate layers are listed in TABLE 1 [24]. From TCAD based strain distribution, it is clearly observed that the flexible TFT on 7 μm thick PI substrate with one CNT buried layer exhibits an applied tensile strain of about 0.70 % on a-IGZO channel, whereas, the applied tensile strain of about 0.40% is observed for the structure with CNT+GO and CNT layer inside PI substrate (2x time larger strain), suggesting that CNT layer might limits/absorb the applied strain and thus, less defect generation inside a-IGZO layer might occur with buried CNT inside PI as compared to conventional PI based flexible TFTs.…”

“…Interestingly, flexible TFTs on buried CNT based PI substrate show a robust electrical performance of only V Th = −0.3 V after the same amount stretching. threshold voltage after mechanical strain/stress are mainly explained by the change of interatomic distance, formation of trap sites, formation of defect states at GI/a-IGZO interface and/or bulk a-IGZO, due to applied external mechanical strain [18]- [24], [29]. In contrast, the robust electrical performance of the flexible oxide TFTs on buried CNT layer based PI substrate might be originated from the presence of buried CNT layer with higher Young's modulus in the middle of PI substrate that might limits the mechanical elongation of the a-IGZO layer.…”

“…Furthermore, the CNT+GO backbone also makes the PI wrinkle-free because the CNT+GO remains being attached to the back side of the PI after detachment [18]. Therefore, the mixture of carbon nanotube (CNT) and graphene oxide (GO) was used as a buffer for nonlaser detach [18]- [21], [23]- [24], [27]. The first PI layer was deposited by the spin-coating process at 2000 rpm for 60 s to achieve a thickness ∼3 μm on top of the CNT+GO layer.…”