Proceedings of the 15th International Conference on Parallel Architectures and Compilation Techniques 2006
DOI: 10.1145/1152154.1152184
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Reducing control overhead in dataflow architectures

Abstract: In recent years, computer architects have proposed tiled architectures in response to several emerging problems in processor design, such as design complexity, wire delay, and fabrication reliability. One of these architectures, WaveScalar, uses a dynamic, tagged-token dataflow execution model to simplify the design of the processor tiles and their interconnection network and to achieve good parallel performance. However, using a dataflow execution model reawakens old problems, including the instruction overhe… Show more

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Cited by 7 publications
(1 citation statement)
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“…In multi-threading the cost of thread creation, termination and switching determines the efficiency of the parallel thread model. This particular field has sought to reduce these costs by combinations of compiler techniques and runtime representations [10], [11] together with hardware support [12], [13]. Closer to home, the implementation of Cilk-5 redesigns its runtime in order to incur the least amount of overhead at execution time.…”
Section: Introduction and Related Workmentioning
confidence: 99%
“…In multi-threading the cost of thread creation, termination and switching determines the efficiency of the parallel thread model. This particular field has sought to reduce these costs by combinations of compiler techniques and runtime representations [10], [11] together with hardware support [12], [13]. Closer to home, the implementation of Cilk-5 redesigns its runtime in order to incur the least amount of overhead at execution time.…”
Section: Introduction and Related Workmentioning
confidence: 99%