Reducing cross-coupling among interconnect wires in deep-submicron datapath design

Abstract

As the CMOS technology enters the deep submicron design era, the lateral inter-wire coupling capacitance becomes the dominant part of load capacitance and makes RC delay on the bus structures very data-dependent.Reducing the crosscoupling capacitance is crucial for achieving high-speed as well as lower power operation. In this paper, we propose two interconnect layout design methodologies for minimizing the "cross-coupling effect' in the design of full-custom datapath. Firstly, we describe the control signal ordering scheme which was shown to minimize the switching power consumption by 10% and wire delay by 15% for a given set of benchmark examples. Secondly, a track assignment algorithm based on evolutionary programming was used to minimize the crosscoupling capacitance. Experimental results have shown that the chip performance improvement as much as 40% can be obtained using the proposed interconnect schemes in various stages of the datapath layout optimization.

Bus encoding to prevent crosstalk delay

“…on the other hand, is intended for use with long, straight buses, and thus these routing schemes are not applicable to our domain of interest. [4] and [5] mention some techniques that are more relevant, such as skewing the timing of signals on adjacent wires, interleaving mutually exclusive buses, and precharging the bus. However, skewing requires careful, technology-dependent circuit design and brings up tricky timing issues, whereas our technique is technology-independent and fully synchronous, with the crosstalk immunity "correct by construction."…”

Optimization of Delay and Energy in On-Chip Buses using Bus Encoding Technique

“…Here the worst case delay is still due to the class 5 transitions, which is high. In [3] a bus encoding is proposed to obtain 10% energy reduction alone with delay reduction of nearly 50%. Bus encoding techniques to reduce the worst case crosstalk delay by nearly 50% are proposed in [2,5].…”

“…In Deep Sub-Micron technology the coupling capacitance exceeds the self capacitance which causes more power consumption and delay on the bus [1]. To sum up, with shrinking the feature sizes, increasing die sizes, scaling of supply voltage, increased interconnect density and faster clock rates, the on-chip buses suffer from high power consumption and large propagation delay due to capacitive crosstalk [2,3]. Since, both power consumed and delay incurred by a system bus increase in the coupling and the self capacitances in modern DSM designs.…”

Coding for system-on-chip networks: a unified framework

“…With shrinking of feature sizes, increasing die sizes, scaling of supply voltage, increasing interconnect density, and faster clock rates, global system-on-chip buses are suffering from large propagation delay due to capacitive crosstalk [3,10,12,13], high power consumption due to both parasitic and coupling capacitance [5,10,15] and increased susceptibility to errors due to DSM noise [4,9]. Coding schemes have been proposed to alleviate these problems.…”