Reducing instruction cache energy consumption using a compiler-based strategy

Abstract

Excessive power consumption is widely considered as a major impediment to designing future microprocessors. With the continued scaling down of threshold voltages, the power consumed due to leaky memory cells in on-chip caches will constitute a significant portion of the processor's power budget. This work focuses on reducing the leakage energy consumed in the instruction cache using a compiler-directed approach.We present and analyze two compiler-based strategies termed as conservative and optimistic. The conservative approach does not put a cache line into a low leakage mode until it is certain that the current instruction in it is dead. On the other hand, the optimistic approach places a cache line in low leakage mode if it detects that the next access to the instruction will occur only after a long gap. We evaluate different optimization alternatives by combining the compiler strategies with state-preserving and state-destroying leakage control mechanisms. We also evaluate the sensitivity of these optimizations to different high-level compiler transformations, energy parameters, and soft errors.

Joint hardware–software leakage minimization approach for the register file of VLIW embedded architectures

“…Some compiler techniques [30] can also be used to turn off several parts of the processor architecture based on the instruction schedule. Some other compiler techniques like [12] exploit the locality of instructions in the instruction memory to reduce the leakage energy consumption. All these techniques are complementary to the proposed approach.…”

“…While various techniques have been developed to reduce the leakage energy in the memories [10][11][12], there has been little research in the area of reducing the leakage energy in register files. In this paper we introduce a novel joint hardware-software method for VLIW embedded architectures that aims to reduce the leakage energy consumed in the register file.…”

Compilation for compact power-gating controls

“…Recent studies have attempted to reduce leakage power using integrated architecture and compiler power-gating mechanisms [Dropsho et al 2002;Rele et al 2002;You et al 2006You et al , 2002Zhang et al 2004Zhang et al , 2003. Dropsho et al [2002] proposed an analytical energy model for architecture-level analysis, and described the benefits of employing a dual-threshold-voltage technique to reduce subthreshold leakage current in the integer functional units of a processor.…”

“…They also proposed an architecture to make power-gating controls applicable to out-of-order issue processors [You et al 2006]. Aside from controlling leakage energy of functional units, Zhang et al [2004] presented a compiler-directed approach that inserts power mode instructions for cache lines to control leakage energy consumed in the instruction cache.…”

Saving Register-File Leakage Power by Monitoring Instruction Sequence in ROB

“…The objective of this monitoring scheme is to find out which register-values causing leakage-power (described above), and to maximize the benefits from register supply-voltage changes. The supply-voltages to a register in this paper include the active mode (1 Volts), drowsy mode (0.3 Volts), and destroy mode (0 Volts), as defined in [3].…”