Reducing leakage energy in FPGAs using region-constrained placement

Gayasen, Aman; Tsai, Yuh-Fang; Narayanan, Vijaykrishnan; Kandemir, Mahmut; Irwin, M.J.; Tuan, Tim

doi:10.1145/968280.968289

Cited by 124 publications

(77 citation statements)

References 22 publications

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“…With this technique, it becomes possible to put unused LUTs and flip-flops to sleep mode independently. Gayasen et al [35] have proposed coarse-grained sleep strategy. In this technique, the entire region of the FPGA is partitioned into logic blocks so that each region can be put into sleep mode independently whenever it is not used.…”

Section: Leakage Power Reductionmentioning

confidence: 99%

Power Efficient Data-Aware SRAM Cell for SRAM-Based FPGA Architecture

Singh¹

2017

Field - Programmable Gate Array

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The design of low-power SRAM cell becomes a necessity in today's FPGAs, because SRAM is a critical component in FPGA design and consumes a large fraction of the total power. The present chapter provides an overview of various factors responsible for power consumption in FPGA and discusses the design techniques of low-power SRAMbased FPGA at system level, device level, and architecture levels. Finally, the chapter proposes a data-aware dynamic SRAM cell to control the power consumption in the cell. Stack effect has been adopted in the design to reduce the leakage current. The various peripheral circuits like address decoder circuit, write/read enable circuits, and sense amplifier have been modified to implement a power-efficient SRAM-based FPGA.

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Section: Leakage Power Reductionmentioning

confidence: 99%

Power Efficient Data-Aware SRAM Cell for SRAM-Based FPGA Architecture

Singh¹

2017

Field - Programmable Gate Array

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“…[9], power gating of logic fabrics was investigated and region-constrained placement was applied to reduce leakage power of unused logic blocks on Xilinx FPGA. Their placement algorithm placed a designed circuit into contiguous regions by utilizing two different styles: hori-zontal and vertical placement.…”

Section: Related Workmentioning

confidence: 99%

Region-Oriented Placement Algorithm for Coarse-Grained Power-Gating FPGA Architecture

Yang

Watanabe

2012

IEICE Trans. Inf. & Syst.

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SUMMARYAn FPGA plays an essential role in industrial products due to its fast, stable and flexible features. But the power consumption of FPGAs used in portable devices is one of critical issues. Top-down hierarchical design method is commonly used in both ASIC and FPGA design. But, in the case where plural modules are integrated in an FPGA and some of them might be in sleep-mode, current FPGA architecture cannot be fully effective. In this paper, coarse-grained power gating FPGA architecture is proposed where a whole area of an FPGA is partitioned into several regions and power supply is controlled for each region, so that modules in sleep mode can be effectively power-off. We also propose a region oriented FPGA placement algorithm fitted to this user's hierarchical design based on VPR [1]. Simulation results show that this proposed method could reduce power consumption of FPGA by 38% on average by setting unused modules or regions in sleep mode.

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“…In [3], various low-leakage techniques, such as redundant SRAM design, dual Vt design, body biasing and gate biasing, are evaluated. As described in [4], cutting off the power supply of an unused region by sleep transistors aims at reducing the logic slice leakage, which occupies 45% of the total leakage in their FPGA, while the assignment of a higher Vt to the configuration SRAM reduces 98% of the SRAM leakage, while increasing the configuration time by 20%. A routing switch in [5] can reduce the leakage current by 40% and 61% in low-power mode and sleep mode, respectively.…”

Section: Introductionmentioning

confidence: 99%

SOTB Implementation of a Field Programmable Gate Array with Fine-Grained Vt Programmability

Hioki

Kobayashi

et al. 2014

JLPEA

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Field programmable gate arrays (FPGAs) are one of the most widespread reconfigurable devices in which various functions can be implemented by storing circuit connection information and logic values into configuration memories. One of the most important issues in the modern FPGA is the reduction of its static leakage power consumption. Flex Power FPGA, which has been proposed to overcome this problem, uses a body biasing technique to implement the fine-grained threshold voltage (Vt) programmability in the FPGA. A low-Vt state can be assigned only to the component circuits along the critical path of the application design mapped on the FPGA, so that the static leakage power consumption can be reduced drastically. Flex Power FPGA is an important application target for the SOTB OPEN ACCESSJ. Low Power Electron. Appl. 2014, 4 189(silicon on thin buried oxide) device, which features a wide-range body biasing ability and the high sensitivity of Vt variation by body biasing, resulting in a drastic subthreshold leakage current reduction caused by static leakage power. In this paper, the Flex Power FPGA test chip is fabricated in SOTB technology, and the functional test and performance evaluation of a mapped 32-bit binary counter circuit are performed successfully. As a result, a three orders of magnitude static leakage reduction with a bias range of 2.1 V demonstrates the excellent Vt controllability of the SOTB transistors, and the 1.2 V bias difference achieves a 50× leakage reduction without degrading speed.Keywords: field programmable gate array (FPGA); static leakage power reduction; fine-grained body biasing; silicon on thin buried oxide (SOTB)

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Reducing leakage energy in FPGAs using region-constrained placement

Cited by 124 publications

References 22 publications

Power Efficient Data-Aware SRAM Cell for SRAM-Based FPGA Architecture

Power Efficient Data-Aware SRAM Cell for SRAM-Based FPGA Architecture

Region-Oriented Placement Algorithm for Coarse-Grained Power-Gating FPGA Architecture

SOTB Implementation of a Field Programmable Gate Array with Fine-Grained Vt Programmability

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