Reducing leakage with mixed-V/sub th/ (MVT)

Sill, Frank; Grassert, Frank; Timmermann, Dirk

doi:10.1109/icvd.2005.147

Cited by 6 publications

(2 citation statements)

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“…Compared to common leakage reduction methods on gate level, the proposed MVT approach uses transistors with different threshold voltages within gates [10,11]. Hence, we can combine the advantages of transistor and gate level solutions.…”

Section: Improved Mixed Gates 41 Mixed Threshold Voltages (Mvt)mentioning

confidence: 97%

“…Moreover, transistor level approaches are not applicable for standard cell design and require long optimization time. Our proposed approach is an improved combination of DTCMOS and Dual-T ox design techniques [10,11]. We combine reduction techniques on transistor and gate level to reduce total static power dissipation, whereas the delay of designs stays the same.…”

Section: Introductionmentioning

confidence: 99%

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Total leakage power optimization with improved mixed gates

Sill

Grassert

Timmermann

2005

Proceedings of the 18th Annual Symposium on Integrated Circuits and System Design - SBCCI '05

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Gate oxide tunneling current I gate and sub-threshold current I sub dominate the leakage of designs. The latter depends on threshold voltage V th while I gate vary with the thickness of gate oxide layer T ox . In this paper, we propose a new method that combines approaches of Dual Threshold CMOS (DTCMOS), mixed-T ox CMOS, and pin-reordering. As the reduction of leakage leads to an increase of gate delay, our purpose is the reduction of total leakage at constant design performance. We modified a given technology and developed a library with a new mixed gate type. Compared to the case where all devices are set to high performance, our approach achieves an average leakage reduction of 65%, whereas design performance stays constant.

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Section: Improved Mixed Gates 41 Mixed Threshold Voltages (Mvt)mentioning

confidence: 97%

Section: Introductionmentioning

confidence: 99%