Gate oxide tunneling current I gate and sub-threshold current I sub dominate the leakage of designs. The latter depends on threshold voltage V th while I gate vary with the thickness of gate oxide layer T ox . In this paper, we propose a new method that combines approaches of Dual Threshold CMOS (DTCMOS), mixed-T ox CMOS, and pin-reordering. As the reduction of leakage leads to an increase of gate delay, our purpose is the reduction of total leakage at constant design performance. We modified a given technology and developed a library with a new mixed gate type. Compared to the case where all devices are set to high performance, our approach achieves an average leakage reduction of 65%, whereas design performance stays constant.

The reduction of leakage power has become an important issue for high performance designs. One way to achieve low-leakage and high performance designs is the use of multi-threshold techniques. In this paper, a new mixed-V th (MVT) CMOS design technique is proposed, which uses different threshold voltages within a logic gate. This new technique allows the reduction of leakage power, while the performance stays constant. A set of algorithms is given assigning optimal distribution of gates. Results indicate that the new MVT approach can provide up to 40% leakage reduction by constant performance compared to dual-V th (DVT) gate-level techniques.

Dynamic circuit techniques offer potential advantages over static CMOS, especially if more complex logic is to be implemented. Therefore, they are extensively used in high performance designs to speed up critical subsystems. However, the speed benefit is traded off for increased power consumption, area overhead, design effort, and reduced noise margins. The continuing process of technology scaling raises further concerns of reliability and limits the wide use of dynamic logic. This paper presents evaluations in terms of area, power dissipation, and propagation delay for several dynamic logic styles as well as for static CMOS in a 90 nm technology. The intention is to assess if dynamic circuit techniques are still an option to boost performance against the background of the issues of nanotechnology. Moreover, issues of reliability and signal integrity, gained from practical experience for different testbenches, and possible solutions are discussed. Finally, an automated design flow for dynamic logic, derived from a standard CMOS flow, is presented.

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