Deep Submicron Technology: Opportunity or Dead End for Dynamic Circuit Techniques

Abstract

Dynamic circuit techniques offer potential advantages over static CMOS, especially if more complex logic is to be implemented. Therefore, they are extensively used in high performance designs to speed up critical subsystems. However, the speed benefit is traded off for increased power consumption, area overhead, design effort, and reduced noise margins. The continuing process of technology scaling raises further concerns of reliability and limits the wide use of dynamic logic. This paper presents evaluations in terms of area, power dissipation, and propagation delay for several dynamic logic styles as well as for static CMOS in a 90 nm technology. The intention is to assess if dynamic circuit techniques are still an option to boost performance against the background of the issues of nanotechnology. Moreover, issues of reliability and signal integrity, gained from practical experience for different testbenches, and possible solutions are discussed. Finally, an automated design flow for dynamic logic, derived from a standard CMOS flow, is presented.

Resistive Computation: A Critique

“…Dynamic logic styles are generally less robust and more susceptible to noise and Process, Voltage, and Temperature (PVT) variations as compared to the static CMOS counterpart [5], and the LUT styles are no exception. The last row in Table 2 shows the normalized delay sensitivity to threshold voltage (Vth) variation.…”

“…The temperature sensitivity will depend on the combined effect of the temperature sensitivities of MTJ resistance and transistor performance. Robustness is one of the major limitations for use of dynamic logic styles in general and this issue gets worse in nano-scale due to increased process variations [5]. Besides reliability issues, dynamic logic styles are not supported by electronic design automation tools in an automated design flow and this further limits the usefulness of MTJ-based LUT styles.…”