Reducing of soft error effects on a MIPS-based dual-core processor

Abstract

In this paper, a simulation-based fault injection analysis of a MIPS-based dual-core processor is presented, an approach is proposed to improve the reliability of most vulnerable parts of the processor components and then the improvement is evaluated. In the first series of experiments, a total of 9100 transient faults were injected in 114 different fault sites of the processor. These experiments demonstrate that the Message Passing Interface, the Arbiter and the Program Counters are the most vulnerable parts of the processor. Thus, these parts were selected as targets for the improvement. The fault tolerance method used for improving the Arbiter is based on using the Triple Modular Redundancy. As for the Message Passing Interface and the Program Counters the single bit error correction Hamming code is used. The experimental results show 11.8% improvement in error recovery and 15.1% reduction of failure rate at the cost of 1.01% area overhead.

A Low-Cost Fault-Tolerant RISC-V Processor for Space Systems

“…In this work, we obtained an average error propagation rate improvement of 50.4% when injecting 10 SEU or SET faults. This result is because the developed processor does not have as many elements susceptible to faults in comparison to the processor described in [6]. Furthermore, the reliable RISC-V core developed by [19] made a test using a neutrons beam and reported an improvement in the mean work to failure of 24x.…”

“…However, the hardened processor was still able to mask some errors, as the error rate in the algorithms reduced between 13% and 21% compared to the processor without fault tolerance techniques. Among the works that evaluate the efficiency of fault tolerance techniques, the work [6] presents an analysis of fault coverage, while others do not present experimental results. In [6], the authors obtained an average error propagation rate improvement of 11.8% when using the processor with fault tolerance techniques.…”

“…Among the works that evaluate the efficiency of fault tolerance techniques, the work [6] presents an analysis of fault coverage, while others do not present experimental results. In [6], the authors obtained an average error propagation rate improvement of 11.8% when using the processor with fault tolerance techniques. In this work, we obtained an average error propagation rate improvement of 50.4% when injecting 10 SEU or SET faults.…”

“…MIPS Crypto [5] applies TMR and matrix encoding techniques to protect its memory buffer units. In [6], the authors employed Hamming code to protect registers and TMR for providing fault tolerance to the messaging interface. These examples illustrate how fault tolerance techniques have been employed in SPARC-and MIPS-based processors.…”

Characterization of a RISC-V System-on-Chip under Neutron Radiation

“…MIPS Crypto [7] uses TMR and matrix encoding techniques to protect its buffer units. MIPSFT [8] employs Hamming code to protect registers and TMR for providing fault tolerance to the message passing interface.…”