Reducing pipeline energy demands with local DVS and dynamic retiming

Abstract

ABSTRACT

Design techniques for variability mitigation

“…Domino logic gates (Sung and Elliott, 2007) and domino latches (Tsai et al, 2011) especially pulsed-latches (Paik et al, 2011) could be used to introduce optimised retiming solutions. Using pulsed-latch instead of Razor latch (Ernst et al, 2003;Lee et al, 2004) may lead to a faster decision about the correctness of propagated data. Augmenting clock skewing techniques (Andrade et al, 2009;Long et al, 2010) for time borrowing can preserve the sequence of pipeline without flushing.…”

“…The error rate is used for power or thermal management through dynamic frequency and voltage scaling (Ernst et al, 2003). Razor (Ernst et al, 2003;Lee et al, 2004) is one of the most common approaches used for power savings by scaling down the supply voltage as low as possible while ensuring correct operation. In contrast to conservative designs, which need conservative margins for the supply voltage, Razor does not need margins as it depends on monitoring the error rate dynamically to adjust the required supply voltage.…”

“…The result of the comparison will be used to compute the error rate, and then the error rate will be used as a feedback to adjust the supply voltage through dynamic voltage scaling. In case of timing error, the correct data will be restored from the shadow latch and all instructions behind the faulty one will be invalidated and the pipeline is restarted after the faulty instruction (Lee et al, 2004). Dynamic retiming is augmented to the Razor approach (Lee et al, 2004) to permit pipeline stages with higher error rates to borrow time from low error rates stages as shown in Figure 14 by using negative and positive clock skew values generated by a programmable local clock controller.…”

“…Source: Lee et al (2004) Although razor introduced a good solution for both retiming and power saving through error detection and correction, it wastes two cycles to detect the error and restore the correct data, and then it flushes all potential incorrect instructions out of the pipeline. It would be better if razor could take the decision earlier not to permit the propagation of wrong data through pipeline stages.…”

Energy-efficient embedded software implementation on multiprocessor system-on-chip with multiple voltages

“…Different from the above, some energy-reduction techniques on single processor have been proposed by Hua et al [2003] for multimedia applications with tolerance to deadline misses while providing a statistical completion ratio guarantee. Lee et al [2004] proposed a local voltage-controller scheme that allows each pipeline stages it's own voltage level and a lower cost-dynamic retiming scheme that incorporates per-stage clock delay elements to allow longer-latency pipeline stages to borrow time from shorter-latency stages. Yuan and Nahrstedt [2003] developed an energy-efficient soft real-time CPU scheduler that allocates CPU cycles periodically to tasks based on statistical demand, rather than worst case, to provide statistical performance guarantees.…”