Reduction of Register File Delay Due to Process Variability in VLIW Embedded Processors

Abstract

Process variation in future technologies can cause severe performance degradation since different parts of the shared Register File (RF) in VLIW processors may operate at various speeds. In this paper we present a complete approach that handles speed variability of the RF proposing different compiletime and run-time design alternatives. The first alternative extends current RF architectures and uses a compile-time variability-aware register assignment algorithm. The second alternative presents a fully-adjustable pure run-time approach, which overcomes the variability loss as well, but at the extra cost of cycles and area. However, the savings achieved and the run-time management of the register delay variations without any support from the user, show a very promising application field. Our results in embedded system benchmarks show that variability can be tackled without significant performance penalty, and trade-offs between performance and area are possible thanks to the whole design spectrum provided by the two presented alternatives. I. INTRODUCTIONNew multimedia consumer applications require high performance embedded platforms due to their intensive processing requirements. In this area of embedded systems, Very Large Instruction Word (VLIW) processors provide a promising solution to achieve suitable performance-power trade-offs. However, transistor scaling in future technology nodes is accompanied by an increase of variability in process technology. Two types of variations exist: functional variation and parametric variation. Functional variation leads to loss in component functionality, while parametric variation leads to timing issues in the working component with respect to its originally designed speed [1], [2], [3].In this paper we present several solutions to handle parametric variation in shared register files of embedded VLIW processors, which provide also trade-offs of precharacterization (design time) effort and dynamic (run-time) overhead for self-tuning. The first solution (Section III) is a hardware/software (HW/SW) approach that relies on limited HW extensions in the Register File (RF), and a modified register assignment phase at compiler level to prevent using marked slow registers. In the latter two approaches (Section IV), we propose further extensions of the RF HW architecture to create completely run-time schemes against dynamic variation in the RF. These run-time approaches do

Compilation for Delay Impact Minimization in VLIW Embedded Systems

“…This limitation makes difficult its extended use. Therefore, we have also designed two additional run-time HW techniques to solve these limitations at the potential cost of reducing system performance [19] (depending on the performance gains achieved by the effective register renaming). These run-time techniques, when compared with the compilation approach presented here, do not reach so optimal results.…”