Redundant logic insertion and fault tolerance improvement in combinational circuits

Abstract

Abstract-This paper presents a novel method to identify and insert redundant logic into a combinational circuit to improve its fault tolerance without having to replicate the entire circuit as is the case with conventional redundancy techniques. In this context, it is discussed how to estimate the fault masking capability of a combinational circuit using the truth-cum-fault enumeration table, and then it is shown how to identify the logic that can introduced to add redundancy into the original circuit without affecting its native functionality and with the aim of improving its fault tolerance though this would involve some trade-off in the design metrics. However, care should be taken while introducing redundant logic since redundant logic insertion may give rise to new internal nodes and faults on those may impact the fault tolerance of the resulting circuit. The combinational circuit that is considered and its redundant counterparts are all implemented in semi-custom design style using a 32/28nm CMOS digital cell library and their respective design metrics and fault tolerances are compared.

A Fault Tolerant Voter for Approximate Triple Modular Redundancy

“…As discussed earlier, some of the internal faults do not propagate to the output owing to the masking capability of the voter circuit. FMR is defined as the ratio of total number of correct voter output states in the presence of internal faults, which are masked, divided by the total number of potential internal fault occurrences [5,8].…”

“…where n, m, and k are the primary inputs, internal nodes, and internal faulty combinations for which a fault is masked at the output, respectively. Here, 2 n represents the non-faulty combinations of nodes, whereas 2 n+m specifies the total number of faulty and non-faulty combinations [5].…”

“…The quest for reliability, the probability of not incurring a failure within the given operation period, has become a vital aspect for circuit designers and manufacturers [3,4]. The International Technology Roadmap for Semiconductors has reported that reliability is a challenge for nano-electronics owing to the technological issues posed by the ever-shrinking semiconductor devices [5]. Thus, the next generation of very deep sub-micron systems will be defined by their reliability and performance [1].…”

Input-Aware Implication Selection Scheme Utilizing ATPG for Efficient Concurrent Error Detection

“…It should be noted that the entire input space does not hold equal significance as some portion of the input space is more vulnerable to errors than the rest [16,17] (i.e., the portion of the input space which makes the maximum number of errors observable at the primary outputs). During the process of generating 32,000 random vectors for assigning detectability to each implication, some of the vectors could be selected from the portion of the input space, which is less vulnerable to errors.…”

Mathematical estimation of logical masking capability of majority/minority gates used in nanoelectronic circuits

“…Moreover, the majority logic function is widely employed [34]- [37] in redundancy architectures which are indeed commonplace in many mission-critical and safety-critical electronic circuit and system designs [38]- [41]. Further, the information about the logical masking capability of a gate may be useful to design digital circuits with improved intrinsic fault tolerance [42]. This tends to assume significance in the context of emerging nanoelectronic designs which are more likely to experience temporary or permanent faults or failures due to radiation and other phenomena [43]- [45].…”