Refractory metal gate processes for VLSI applications

Shah, P.

doi:10.1109/t-ed.1979.19470

Cited by 60 publications

(9 citation statements)

References 8 publications

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“…Adhesion to the gate dielectric films appears to be a problem for some refractory metal films. Although evaporated and sputtered Mo films showed good adhesion on Si02, evaporated W films peeled off after 1000°C anneal on Si02 and was attributed to high internal stresses [29]. Refractory materials also tend to have fairly high amount of stress which is dependent on the deposition method, thickness of the film, microstructure, phase transformation, thermal budget and thermal properties of surrounding materials [12, 25 30-31].…”

Section: Thermal Chemical and Mechanical Stabilitymentioning

confidence: 99%

Metal gates for advanced CMOS technology

Maiti

Tobin

1999

SPIE Proceedings

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This paper will provide an overview of the emerging trends in metal gate solutions for advanced CMOS technology. Performance enhancement in silicon-based CMOS technology through MOSFET scaling has shown some limitations with the current polysilicon gate electrode. Replacing polysilicon gate electrode by metal appears to be promising. However, the choice of the metal gate material depends on its work function (single or dual metal gates), thermal/chemical stability with surrounding materials, process integration (conventional or inlaid approach), deposition process, resistivity, and eventually performance, reliability and future scaling. This paper will discuss some of the results published in the literature that address some of these issues and propose future directions. Single mid-gap metal gate approach appears to be simpler from an integration point of view but achieving low MOSFET threshold voltage is a concern. Some channel engineering approaches have been reported to address this issue. Dual metal gate approach with work function similar to n and p doped poly-Si appears ideal, although processing complexity could be a hindrance. Also the need for inlaid gate integration could be enhanced because of thermal/chemical stability effects of metal gate electrode with underlying gate dielectric, the inability to etch new materials or to reduce device instability due to film stress as in the conventional approach. The performance improvement of CMOS devices has been estimated with metal gates along with reliability issues.

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Section: Thermal Chemical and Mechanical Stabilitymentioning

confidence: 99%

Metal gates for advanced CMOS technology

Maiti

Tobin

1999

SPIE Proceedings

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“…F OR A long time, metal silicides had proven valuable to both ohmic and Schottky contacts. Aside from applications as ohmic or Schottky contacts, high conductivity metal silicides were proposed in 1979 as contacts to doped polysilicon or polycide structure to reduce resistance and give extra interconnection capability [1]. In 1981, the concept was extended to diffusion areas by forming self-aligned silicide at both polysilicon and diffusion areas simultaneously for improving both contact and interconnects [2].…”

Section: Introductionmentioning

confidence: 99%

Improving the electrical integrity of Cu-CoSi/sub 2/ contacted n/sup +/p junction diodes using nitrogen-incorporated Ta films as a diffusion barrier

Yang

You

et al. 2002

IEEE Trans. Electron Devices

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The study on improving the electrical integrity of Cu-CoSi 2 contacted-junction diodes by using the reactively sputtered TaN as a diffusion barrier is presented in this paper. In this study, the Cu(300 nm)-CoSi 2 (50 nm)/n + p junction diodes were intact with respect to metallurgical reaction up to a 350 C thermal annealing while the electrical characteristics started to degrade after annealing at 300 C in N 2 ambient for 30 min. With the addition of a 50-nm-thick TaN diffusion barrier between Cu and CoSi 2 , the junction diodes were able to sustain annealing up to 600 C without losing the basic integrity of the device characteristics, and no metallurgical reaction could be observed even after a 750 C annealing in furnace. In addition, the structure of TaN layers deposited on CoSi 2 at various nitrogen flow rates has been investigated. The TaN film with small grain sizes deposited at nitrogen flow ratios exceeding 10% shows better barrier capability against Cu diffusion than the others.

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“…However, few papers have reported on implantation in tungsten (1)(2)(3). Impurity profile measurements in tungsten cannot easily be carried out by Rutherford backscattering spectrometry (RBS) measurement, because the observed spectra of ion implanted species overlap with that of tungsten (4).…”

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confidence: 99%

Ion Implantation in Tungsten Layers

Hara¹,

Chen²,

Ando³

1987

J. Electrochem. Soc.

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Impurity concentration profiles of arsenic ion implantation in sputtered and chemical vapor deposited (CVD) tungsten layers are studied. Arsenic impurity profiles in tungsten and silicon are measured using Rutherford backscattering and secondary ion mass spectrometries. Projected range and projected range straggle for both layers are obtained from these profiles. A smaller projected range straggle, indicating narrower impurity profiles is attained in the CVD layer when compared with that in sputtered layer. However, these values are much greater than those predicted by the LSS theory. Profile tailing appearing at lower concentrations in through tungsten implantation is also studied from carrier concentration profile measurement in silicon. Profile tailing appearing at low concentrations is specifically evident in sputtered layers. However, it does not appear in the CVD layer. Since the penetration of ion implanted species can be suppressed markedly in the CVD tungsten layer, this layer is a promising material for the self-aligned gate process.Ion implantation in tungsten is being looked at as an important approach in the self-aligned gate process. However, few papers have reported on implantation in tungsten (1-3). Impurity profile measurements in tungsten cannot easily be carried out by Rutherford backscattering spectrometry (RBS) measurement, because the observed spectra of ion implanted species overlap with that of tungsten (4). Impurity profile calibration is needed in secondary ion mass spectrometry (SIMS) measurement.Computer simulation has produced an optimized layer structure without spectrum overlapping (4). The measurement for the optimized layer gives exact impurity profiles in tungsten employing RBS. Iwata et al. (5) reported a sputtered tungsten gate process, where penetration of ion-implanted species through W/SiOJSi was observed by SIMS. It has been reported that chemically vapor deposited (CVD) tungsten shows better thermal stability (6-8). Recently, selective tungsten deposition by CVD for via contact holes has been studied by many authors (9-11). Ion implantation is an important process in the ohmic contact application as well as in the selfaligned gate process. However, few papers have reported ion implantation in CVD tungsten.Delfino and DeBlasi (2) studied B and BF2 implantation in silicon through ll0A thick selective tungsten films. Carrier concentration profiles in silicon were observed. They reported sufficient stopping power and an ineffectiveness in eliminating axial boron channeling (3, 12) Tsaur et al. (12) studied the formation of selective tungsten silicide by arsenic ion beam mixing, employing rapid thermal annealing.A study of the ion implantation profile in tungsten, and determination of projected range Rp and projected range straggle ARp, which are required in th}s application, have not yet been reported.This paper describes ion implantation in sputtered and CVD tungsten layers. Arsenic impurity profiles in tungsten and silicon observed by RBS and SIMS are shown. Experimental Pro...

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Refractory metal gate processes for VLSI applications

Cited by 60 publications

References 8 publications

Metal gates for advanced CMOS technology

Metal gates for advanced CMOS technology

Improving the electrical integrity of Cu-CoSi/sub 2/ contacted n/sup +/p junction diodes using nitrogen-incorporated Ta films as a diffusion barrier

Ion Implantation in Tungsten Layers

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