Regional congestion awareness for load balance in networks-on-chip

Gratz, Paul V.; Grot, Boris; Keckler, Stephen W.

doi:10.1109/hpca.2008.4658640

Cited by 306 publications

(262 citation statements)

References 27 publications

Supporting

Mentioning

253

Contrasting

Order By: Relevance

“…In this perspective, the use of virtual channels and dynamic traffic distribution [15] allows to reduce contention, improve throughput and provide fault-tolerance. The proposed approach has two main differences with respect to these works.…”

Section: Noc-based Power-performance Optimizationsmentioning

confidence: 99%

A control-based methodology for power-performance optimization in NoCs exploiting DVFS

Zoni

Terraneo

Fornaciari

2015

Journal of Systems Architecture

View full text Add to dashboard Cite

a b s t r a c tNetworks-on-Chip (NoCs) are considered a viable solution to fully exploit the computational power of multi-and many-cores, but their non negligible power consumption requires ad hoc power-performance design methodologies. In this perspective, several proposals exploited the possibility to dynamically tune voltage and frequency for the interconnect, taking steps from traditional CPU-based power management solutions. However, the impact of the actuators, i.e. the limited range of frequencies for a PLL (Phase Locked Loop) or the time to increase voltage and frequency for a Dynamic Voltage and Frequency Scaling (DVFS) modules, are often not carefully accounted for, thus overestimating the benefits. This paper presents a control-based methodology for the NoC power-performance optimization exploiting the Dynamic Frequency Scaling (DFS). Both timing and power overheads of the actuators are considered, thanks to an ad hoc simulation framework. Moreover the proposed methodology eventually allows for user and/or OS interactions to change between different high level power-performance modes, i.e. to trigger performance oriented or power saving system behaviors. Experimental validation considered a 16-core architecture comparing our proposal with different settings of threshold-based policies. We achieved a speedup up to 3 for the timing and a reduction up to 33.17% of the power ⁄ time product against the best threshold-based policy. Moreover, our best control-based scheme provides an averaged power-performance product improvement of 16.50% and 34.79% against the best and the second considered threshold-based policy setting.

show abstract

Section: Noc-based Power-performance Optimizationsmentioning

confidence: 99%

A control-based methodology for power-performance optimization in NoCs exploiting DVFS

Zoni

Terraneo

Fornaciari

2015

Journal of Systems Architecture

View full text Add to dashboard Cite

show abstract

“…Second, intra-and inter-application interference should be minimized. RCA [22] utilizes global network information but does not consider interference. DBSS offers a middle ground between these extremes.…”

Section: Ieee Transactions On Computersmentioning

confidence: 99%

“…RCA is the first work utilizing global information to improve load balancing in NoCs [22]. However, it introduces interference.…”

Section: Introductionmentioning

confidence: 99%

“…A local selection strategy leverages only the status of neighboring nodes, which tends to violate the global balance intrinsic to traffic [22]. Globally adaptive selection strategies, such as Regional Congestion Awareness (RCA) [22], utilize a dedicated network to gather global information; it introduces excess information when selecting the output port and offers no isolation among applications, leading to performance degradation for consolidated workloads. This excess information can be classified as intra-and inter-application interference.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Holistic Routing Algorithm Design to Support Workload Consolidation in NoCs

Jerger

Wang

et al. 2014

IEEE Trans. Comput.

View full text Add to dashboard Cite

Abstract-To provide efficient, high-performance routing algorithms, a holistic approach should be taken. The key aspects of routing algorithm design include adaptivity, path selection strategy, VC allocation, isolation and hardware implementation cost; these design aspects are not independent. The key contribution of this work lies in the design of a novel selection strategy, Destination-Based Selection Strategy (DBSS) which targets interference that can arise in many-core systems running consolidation workloads. In the process of this design, we holistically consider all aspects to ensure an efficient design. Existing routing algorithms largely overlook issues associated with workload consolidation. Locally adaptive algorithms do not consider enough status information to avoid network congestion. Globally adaptive routing algorithms attack this issue by utilizing network status beyond neighboring nodes. However, they may suffer from interference, coupling the behavior of otherwise independent applications. To address these issues, DBSS leverages both local and non-local network status to provide more effective adaptivity. More importantly, by integrating the destination into the selection procedure, DBSS mitigates interference and offers dynamic isolation among applications. Results show that DBSS offers better performance than the best baseline selection strategy and improves the energy-delay product for medium and high injection rates; it is well suited for workload consolidation.

show abstract

“…Ming Li et al [9] introduced congestion-aware dynamic routing algorithm DyXY that determines output channel on the basis of congestion status of buffers of adjacent nodes. RCA [10], DAR [11], DBAR [12] and CATRA [13] are congestion-aware fully adaptive routing algorithms that use non-local congestion information to route the packet using extra hardware.…”

Section: Related Workmentioning

confidence: 99%

CARM: Congestion Adaptive Routing Method for On Chip Networks

Kumar

Laxmi

Gaur

et al. 2014

2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems

View full text Add to dashboard Cite

Abstract-Network-on-Chip (NoC) has emerged as a longterm and efficient on-chip communication solution for MCSoC and CMP micro-architectures to overcome bottleneck of traditional bus-based interconnects. Performance of NoC is highly dependent on routing algorithm we choose. In this paper, we present a highly adaptive and deadlock free routing algorithm for 2D mesh topology to mitigate congestion. Proposed algorithm provides a high degree of adaptiveness by allowing cycles in channel dependency graph and using one additional virtual channel along the Y dimension only. It uses all available minimal/non-minimal paths between source and destination nodes. A packet is routed along the non-minimal path only when minimal paths get congested at the neighboring nodes. Results show that proposed congestion-aware routing algorithm improves network performance by routing packets through non-congested areas.

show abstract

Regional congestion awareness for load balance in networks-on-chip

Cited by 306 publications

References 27 publications

A control-based methodology for power-performance optimization in NoCs exploiting DVFS

A control-based methodology for power-performance optimization in NoCs exploiting DVFS

Holistic Routing Algorithm Design to Support Workload Consolidation in NoCs

CARM: Congestion Adaptive Routing Method for On Chip Networks

Contact Info

Product

Resources

About