Register allocation and binding for low power

Chang, Jui-Ming; Pedram, Massoud

doi:10.1145/217474.217502

Cited by 144 publications

(162 citation statements)

References 14 publications

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“…Separate CGs are created for the registers and FUs. The edge weights between two nodes represent the switching cost when these two nodes are executed one after the other in the same FU [24]. The power-related metrics [4] are based on the edge weights of the compatibility graph and are defined as follows: m 1 = total number of edges in the graph, m 2 = average of edge weights for the lowest k% in the value range for each node where k is user-defined m 3 = average of all edge weights (i.e., m 2 for k = 100%).…”

Section: Power Costmentioning

confidence: 99%

A Novel Framework for Applying Multiobjective GA and PSO Based Approaches for Simultaneous Area, Delay, and Power Optimization in High Level Synthesis of Datapaths

2012

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High-Level Synthesis deals with the translation of algorithmic descriptions into an RTL implementation. It is highly multiobjective in nature, necessitating trade-offs between mutually conflicting objectives such as area, power and delay. Thus design space exploration is integral to the High Level Synthesis process for early assessment of the impact of these trade-offs. We propose a methodology for multi-objective optimization of Area, Power and Delay during High Level Synthesis of data paths from Data Flow Graphs (DFGs). The technique performs scheduling and allocation of functional units and registers concurrently. A novel metric based technique is incorporated into the algorithm to estimate the likelihood of a schedule to yield low-power solutions. A true multi-objective evolutionary technique, "Nondominated Sorting Genetic Algorithm II" (NSGA II) is used in this work. Results on standard DFG benchmarks indicate that the NSGA II based approach is much faster than a weighted sum GA approach. It also yields superior solutions in terms of diversity and closeness to the true Pareto front. In addition a framework for applying another evolutionary technique: Weighted Sum Particle Swarm Optimization (WSPSO) is also reported. It is observed that compared to WSGA, WSPSO shows considerable improvement in execution time with comparable solution quality.

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Section: Power Costmentioning

confidence: 99%

A Novel Framework for Applying Multiobjective GA and PSO Based Approaches for Simultaneous Area, Delay, and Power Optimization in High Level Synthesis of Datapaths

2012

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“…Most previous work on high-level synthesis tackles datadominated behaviors [1,2], normally found in digital signal processing and image processing applications. These behaviors are characterized by a predominance of arithmetic operations and an absence of control flow.…”

Section: Related Workmentioning

confidence: 99%

A comprehensive high-level synthesis system for control-flow intensive behaviors

Wang

Tan

Luo

et al. 2003

Proceedings of the 13th ACM Great Lakes Symposium on VLSI

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In this paper, we describe a comprehensive high-level synthesis system for control-flow intensive as well as data-dominated behaviors. We propose a new control-data flow graph model to preserve the parallelism inherent in the application, as well as to facilitate high-level synthesis. Our algorithm, which is based on an iterative improvement strategy, performs clock selection, scheduling, module selection, resource allocation and assignment simultaneously to fully derive the benefits of design space exploration at the behavior level. The system can be used to optimize area, power or energy, by selecting the cost function accordingly. Experimental results show that for energy-optimized designs, energy is reduced by up to 79.4% (an average of 42.2%), with an average of 24.8% area overhead, compared to area-optimized designs. For power-optimized designs, power is reduced by up to 70.8% (an average of 56.7%), with an average of 25.2% area overhead, compared to area-optimized designs. No V dd scaling is performed to obtain the above results.

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“…Recently, new research directions in reducing power consumptions have begun to address the issues on the aspect of architecture designs and on software arrangements at instruction-level to help reduce power consumptions. [1,5,8,11,12,17,19,20]. In order to reduce the dynamic power, several research work have been proposed to reduce the dissipation.…”

Section: Introductionmentioning

confidence: 99%

“…In order to reduce the dynamic power, several research work have been proposed to reduce the dissipation. For example, software rearrangements to utilize the value locality of registers [5], the swapping of operands for booth multiplier [12], the scheduling of VLIW instructions to reduce the power consumption on the instruction bus [11], gating clock to reduce workloads [8,19,20], cache sub-banking mechanism [17], the utilization of instruction cache [1], etc.…”

Section: Introductionmentioning

confidence: 99%

A sink-n-hoist framework for leakage power reduction

You

Huang

Lee

2005

Proceedings of the 5th ACM International Conference on Embedded Software

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Power leakage constitutes an increasing fraction of the total power consumption in modern semiconductor technologies. Recent research efforts have tried to integrate architecture and compiler solutions to employ power-gating mechanisms to reduce leakage power. This approach is to have compilers perform data-flow analysis and insert instructions at programs to shut down and wake up components whenever appropriate for power reductions. While this approach has been shown to be effective in early studies, there are concerns for the amount of power-control instructions being added to programs with the increasing amount of components equipped with power-gating control in a SoC design platform. In this paper, we present a Sink-N-Hoist framework in the compiler solution to generate balanced scheduling of power-gating instructions. Our solution will attempt to merge power-gating instructions as one compound instruction. Therefore, it will reduce the amount of power-gating instructions issued. We perform experiments by incorporating our compiler analysis and scheduling policies into SUIF compiler tools and by simulating the energy consumptions on Wattch toolkits. The experimental results demonstrate that our mechanisms are effective in reducing the amount of power-gating instructions while further in reducing leakage power compared to previous methods.

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Register allocation and binding for low power

Cited by 144 publications

References 14 publications

A Novel Framework for Applying Multiobjective GA and PSO Based Approaches for Simultaneous Area, Delay, and Power Optimization in High Level Synthesis of Datapaths

A Novel Framework for Applying Multiobjective GA and PSO Based Approaches for Simultaneous Area, Delay, and Power Optimization in High Level Synthesis of Datapaths

A comprehensive high-level synthesis system for control-flow intensive behaviors

A sink-n-hoist framework for leakage power reduction

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