Register allocation for software pipelined loops

Rau, B. Ramakrishna; Lee, M.; Tirumalai, P.; Schlansker, Michael

doi:10.1145/143103.143141

Cited by 60 publications

(83 citation statements)

References 14 publications

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“…It is general enough to allow many variants for register optimisation methods: for instance, a variant may correspond to a particular shape of the reuse graph, or to a specific technique for computing it. It allows to model buffer optimisation problem (Ning and Gao, 1993), as well as rotating register files (Rau et al, 1992). Later, these two variants have been studied in (Touati and Eisenbeis, 2004) and will be compared to our new heuristic.…”

Section: Related Workmentioning

confidence: 99%

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SIRALINA: efficient two-steps heuristic for storage optimisation in single period task scheduling

2010

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Abstract. In this paper, we study the general problem of one-dimensional periodic task scheduling under storage requirement, irrespective of machine constraints. We have already presented in (Touati and Eisenbeis, 2004) a theoretical framework that allows an optimal optimisation of periodic storage requirement in a cyclic schedule. Since our optimization problem is NP-hard (Touati, 2002), solving an exact integer linear programming formulation is too expensive in practice. In this article, we propose an efficient two-steps heuristic using model's properties that allows fast computation times while providing highly satisfactory results. This method includes the solution of an integer linear program with a totally unimodular constraints matrix in first step, then the solution of a linear assignment problem. Our heuristic is implemented for an industrial compiler for embedded VLIW processors.

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Section: Related Workmentioning

confidence: 99%

“…− Method 5 is a variant of (Rau et al, 1992). It starts by first pre-fixing an arbitrary Hamiltonian reuse circuit, then it minimises µ i,j .…”

Section: Frameworkmentioning

confidence: 99%

SIRALINA: efficient two-steps heuristic for storage optimisation in single period task scheduling

2010

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“…A rotating register file [3,13,16] is a hardware feature that moves (shift) implicitly architectural registers in a cyclic way. At every new kernel issue (special branch operation), each architectural register specified by program is mapped by hardware to a new physical register.…”

Section: Rotating Register Filesmentioning

confidence: 99%

“…Indeed, if we succeed in building a software pipelined schedule that does not produce more than R values simultaneously alive, then we can build a cyclic register allocation with R available registers [2,13]. We can use either loop unrolling [2], inserting move operations [7], or a hardware rotating register file when available [13] 2 . Therefore, a great amount of work tries to schedule a loop such that it does not use more than R values simultaneously alive [8,22,12,14,11,4,15,6,9].…”

Section: Introductionmentioning

confidence: 99%

Early Control of Register Pressure for Software Pipelined Loops

Touati

Eisenbeis

2003

Lecture Notes in Computer Science

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Abstract. The register allocation in loops is generally performed after or during the software pipelining process. This is because doing a conventional register allocation at first step without assuming a schedule lacks the information of interferences between variable lifetime intervals. Thus, the register allocator may introduce an excessive amount of false dependences that reduce dramatically the ILP (Instruction Level Parallelism). We present a new framework for controlling the register pressure before software pipelining. This is based on inserting some anti-dependences edges (register reuse edges) labeled with reuse distances, directly on the data dependence graph. In this new graph, we are able to guarantee that the number of simultaneously alive variables in any schedule does not exceed a limit. The determination of register and distance reuse is parameterized by the desired critical circuit ratio (MII) as well as by the register pressure constraints -either can be minimized while the other one is fixed. After scheduling, register allocation is done cyclically on conventional register sets or on rotating register files. We give an optimal exact model, and another approximative one that generalizes the Ning-Gao [12] buffer optimization heuristics.

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“…In this case, the schedule is unfeasible and some actions must be taken in order to reduce the register pressure. Some possible solutions outlined in [25] and evaluated in [17] are:…”

Section: Introductionmentioning

confidence: 99%

Modulo scheduling with reduced register pressure

Llosa

Valero

Agyuade

et al. 1998

IEEE Trans. Comput.

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Abstract-Software pipelining is a scheduling technique that is used by some product compilers in order to expose more instruction level parallelism out of innermost loops. Modulo scheduling refers to a class of algorithms for software pipelining. Most previous research on modulo scheduling has focused on reducing the number of cycles between the initiation of consecutive iterations (which is termed II) but has not considered the effect of the register pressure of the produced schedules. The register pressure increases as the instruction level parallelism increases. When the register requirements of a schedule are higher than the available number of registers, the loop must be rescheduled perhaps with a higher II. Therefore, the register pressure has an important impact on the performance of a schedule. This paper presents a novel heuristic modulo scheduling strategy that tries to generate schedules with the lowest II, and, from all the possible schedules with such II, it tries to select that with the lowest register requirements. The proposed method has been implemented in an experimental compiler and has been tested for the Perfect Club benchmarks. The results show that the proposed method achieves an optimal II for at least 97.5 percent of the loops and its compilation time is comparable to a conventional top-down approach, whereas the register requirements are lower. In addition, the proposed method is compared with some other existing methods. The results indicate that the proposed method performs better than other heuristic methods and almost as well as linear programming methods, which obtain optimal solutions but are impractical for product compilers because their computing cost grows exponentially with the number of operations in the loop body.

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Register allocation for software pipelined loops

Cited by 60 publications

References 14 publications

SIRALINA: efficient two-steps heuristic for storage optimisation in single period task scheduling

SIRALINA: efficient two-steps heuristic for storage optimisation in single period task scheduling

Early Control of Register Pressure for Software Pipelined Loops

Modulo scheduling with reduced register pressure

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