Relationship between amplifier settling time and pole-zero placements for second-order systems

Gupta

2014 2nd International Conference on Emerging Technology Trends in Electronics, Communication and Networking

et al. 2014

This work presents the design and simulation of a low power CMOS Sample and Hold OTA for a 16bit, 5Ms/S pipelined ADC. The designing of high precision amplifiers is challenging in modern CMOS process. It drives ADC design methodology towards advance calibration approaches and compromised with low SNR. This paper deals with advance design techniques for High gain like triple cascode and achieves a DC gain of 132 dB and 68 MHz unity gain bandwidth with a phase margin of 88 degrees while driving the 16pf load of the first stage. Transient response of Charge Redistribution SHA shows settling accuracy of 15µV in 66 nanoseconds while consuming 20mW power. Switched capacitor CMFB has been implemented for the gain boosting amplifiers and main stage amplifier respectively. The design has been implemented in UMC 0.18µm technology. Design methodology for high gain and better settling performance at low power are also discussed in detail.

Section: B Frequency Domain Pole Zero and Bandwidth Analysismentioning

confidence: 99%

Design of sample and hold for 16 bit 5 Ms/S pipeline analog to digital converter

Gupta

2014 2nd International Conference on Emerging Technology Trends in Electronics, Communication and Networking

et al. 2014

IEEE Trans. Circuits Syst. I

“…Effects of will be shown for the class-A and class-AB circuits, respectively, in the following paragraph. During the hold phase is added to the differential input voltage, , leading to (20) and (21) Low order harmonic distortion components can be found for the class-A circuit to be equal to HD (22) HD (23) and HD (24) where represent the amplitude of the sinusoidal input current . For the case of the class-AB CSH circuit, it can be found that HD (25) and…”

Section: ) Static Offset Voltagementioning

confidence: 99%

Analysis and Design of a Low-Voltage, Low-Power, High-Precision, Class-AB Current-Mode Subthreshold CMOS Sample and Hold Circuit

Sawigun

Serdijn

2011

This paper proposes the design of a current-mode sample and hold circuit using subthreshold MOSFETs. The proposed circuit combines negative feedback and the compressive characteristic of a class-AB weak inversion transconductor to achieve low switching error, high signal-to-noise ratio and high dynamic range from a low supply voltage and very low current consumption. The paper also provides a feedback analysis of current mode sample and hold circuits. Several design issues including circuit stability, mismatch, linearity, noise, and power consumption are discussed and a comparison of class-A and class-AB versions of subthreshold sample and hold circuits is made. The design verification of the proposed class-AB current mode sample and hold circuit is done by circuit simulations using 0.13 m CMOS model parameters. The results show that, from a 0.6 V supply and with a power consumption of 27.5 nW, the proposed circuit provides 73 dB signal-to-noise ratio, 77 dB dynamic range, and a figure of merit of 1.9 nW/MHz.

IEEE Trans. Circuits Syst. I

“…For an error of 2%, . The settling time of can be derived from the following relation: (26) Substituting (12) and (18) into the left side of this relation, we have (27) The settling time for function can be determined from this equation and is given by (28) From this last relation, it is possible to calculate the exponential variation rate of the functions , , and . Using (25) and (28), the exponential variation rate can be written as (29) If and are known, may be readily determined.…”

Section: E Functions Restrictionsmentioning

confidence: 99%

A New Class of Continuous-Time Delay-Compensated Parameter-Varying Low-Pass Elliptic Filters With Improved Dynamic Behavior

Piskorowski¹,

Anda

2009

In some applications, it is required to have continuous-time low-pass analog filtering systems which simultaneously possess a constant group delay in the passband and a narrow transition band. Usually, these systems are implemented by adding to the output of a filter with steep-amplitude selectivity (an elliptic filter, for instance) an all-pass filter which compensates the unfavorable run of the group delay response of the first filter. However, this compensation process will also increase the duration of the transient response of the resulting filtering system. This paper presents a new class of delay-compensated parameter-varying lowpass elliptic filters with a transient response of short duration. This improvement is achieved by means of a temporary change in the value of the filter parameters when a steplike transition with a minimum amplitude is detected in the input signal. As a consequence of the control strategy used to induce parameter variations in the proposed class of filters, its behavior is nonlinear in nature. Therefore, its stability properties (and particularly their bounded-input bounded-output stability) are also assessed. Simulations verifying the effectiveness of the new class of filters are presented and compared to the performance of delay-compensated and delay-uncompensated elliptic filters which were chosen as study cases.