Reliability analysis of a fault-tolerant RISC-V system-on-chip

Santos, Douglas A.; Luza, Lucas Matana; Dilillo, Luigi; Zeferino, Cesar Albenes; Melo, Douglas Rossi de

doi:10.1016/j.microrel.2021.114346

Cited by 20 publications

(29 citation statements)

References 20 publications

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“…RISC-V is an open and extendable ISA that has gained growing interest in academia and industry since its introduction in 2010 [33]. Numerous RISC-V cores have been implemented for embedded system applications [16], [34], [35], and RISC-V has recently received attention for space applications, opening the way for the development of fault-tolerant RISC-V microarchitectures [6], [17], [28], [36], [37]. Table 1 summarizes the most representative RISC-V-based FT works, categorized by the applied techniques, hardened microarchitecture components, and verification/test methodology.…”

Section: Risc-v Fault-tolerant Processor Coresmentioning

confidence: 99%

Design and Evaluation of Buffered Triple Modular Redundancy in Interleaved-Multi-Threading Processors

et al. 2022

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Fault management in digital chips is a crucial aspect of functional safety. Significant work has been done on gate and microarchitecture level triple modular redundancy, and on functional redundancy in multi-core and simultaneous-multi-threading processors, whereas little has been done to quantify the fault tolerance potential of interleaved-multi-threading. In this study, we apply the temporal-spatial triple modular redundancy concept to interleaved-multi-threading processors through a design solution that we call Buffered triple modular redundancy, using the soft-core Klessydra-T03 as the basis for our experiments. We then illustrate the quantitative findings of a large fault-injection simulation campaign on the fault-tolerant core and discuss the vulnerability comparison with previous representative fault-tolerant designs. The results show that the obtained resilience is comparable to a full triple modular redundancy at the cost of execution cycle count overhead instead of hardware overhead, yet with higher achievable clock frequency.INDEX TERMS Circuit faults, digital integrated circuits, fault detection, fault tolerant computing, field programmable gate arrays, microprocessors, multithreading, radiation hardening (electronics), redundancy, robustness.Open Access funding provided by 'Università degli Studi di Roma ''La Sapienza''' within the CRUI CARE Agreement

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Section: Risc-v Fault-tolerant Processor Coresmentioning

confidence: 99%

Design and Evaluation of Buffered Triple Modular Redundancy in Interleaved-Multi-Threading Processors

et al. 2022

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“…The proposed Hardened RISC-V (HARV) processor [18], and its subsequent extension to an SoC [15] (here referred to as HARV-SoC), rely on hardening strategies to meet the requirements of critical applications targeting harsh environments. At the architectural level, the most critical parts of a Central Processing Unit (CPU) are the control unit, program counter, instruction register, register file, and the Arithmetic Logic Unit (ALU), as they can cause critical failures when affected by SEEs [6].…”

Section: Fault-tolerant Risc-v System-on-chipmentioning

confidence: 99%

“…We adopted these techniques due to their wide employment in related work [19]- [22]. Also, their combination results in a robust and cost-effective hardening strategy, as shown in [15], [17].…”

Section: Fault-tolerant Risc-v System-on-chipmentioning

confidence: 99%

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Neutron Irradiation Testing and Analysis of a Fault-Tolerant RISC-V System-on-Chip

Santos

Mattos

Luza

et al. 2022

2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)

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The radiation in harsh environments affects electronic systems, inducing permanent and temporary errors. These effects lead to unpredictable behaviors detrimental to critical applications and fail-safe systems. This work evaluates the reliability of a fault-tolerant RISC-V System-on-Chip (SoC) under atmospheric neutron irradiation in a particle accelerator. Prior work has analyzed the effectiveness of the hardening techniques of this SoC in simulation and provided a preliminary characterization in an irradiation facility. The applied hardening techniques showed a significant reliability improvement compared to the unhardened implementation of the SoC. The system executed a performance benchmark as workload, which finished correctly in most runs despite suffering from Single Event Effects (SEEs). This work presents a detailed analysis of the experimental results, reporting error rates and classification, extending the analysis given in previous works. Finally, a comprehensive discussion of implementation limitations and the proposition of further improvements are provided.

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“…The works differentiate an NMR domain for pipeline resources and an ECC domain for memories and the register file. Similarly, [13] and [14] enhance an areaoptimized RISC-V implementation with Hamming codes on the register file and replicate the ALU as TMR.…”

Section: Related Workmentioning

confidence: 99%

A Framework for Fault Tolerance in RISC-V

Dorflinger

Kleinbeck

Albers

et al. 2022

2022 IEEE Intl Conf on Dependable, Autonomic and Secure Computing, Intl Conf on Pervasive Intelligence and Computing, Intl Conf

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Microcontrollers require protection against transient and permanent faults when being utilized for safetycritical and highly reliable applications. Fail safe Dual Core Lockstep architectures are widely used in the automotive domain; the aerospace domain utilizes fail functional TMR or higher redundancy. This work incorporates fault tolerance techniques of those domains into a framework for RISC-V processors. The implemented fault tolerance components are highly configurable to satisfy various dependability requirements. The cost of applied fault tolerance mechanisms is evaluated for both an FPGA and an ASIC implementation. Fault injection tests prove the effectiveness for error detection and cover both transient and permanent faults in logic and memories. New methods are introduced to minimize the error detection latency and achieve a reduction of up to 79%.

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Reliability analysis of a fault-tolerant RISC-V system-on-chip

Cited by 20 publications

References 20 publications

Design and Evaluation of Buffered Triple Modular Redundancy in Interleaved-Multi-Threading Processors

Design and Evaluation of Buffered Triple Modular Redundancy in Interleaved-Multi-Threading Processors

Neutron Irradiation Testing and Analysis of a Fault-Tolerant RISC-V System-on-Chip

A Framework for Fault Tolerance in RISC-V

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