Reliability Aspects of a Floating Gate E2 PROM

Euzent, B.L.; Boruta, Nick; Lee, Jimmy; Jenq, C.S.

doi:10.1109/irps.1981.362965

Cited by 22 publications

(8 citation statements)

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“…At first glance, such charges should result in a constant shift of both V T levels, while the actual behavior features a milder dependence on N C by the programmed V T with respect to the erased one, pointing toward an interplay among different mechanisms. This picture is confirmed by early results on different non-volatile memory technologies, where different P/E schemes (i.e., different electron injection conditions into the oxide) resulted in different V T dependences on N C [70]. A thorough analysis of the phenomenon was first conducted in [71], using charge-pumping and V T measurements to assess the roles of interface and oxide charges, and was later corroborated by subsequent studies [72].…”

Section: Endurancementioning

confidence: 55%

“…In particular, it was found that a ten-year retention requirement could be satisfied with a minimum tunnel oxide thickness around 3.5-4.5 nm [56,165], much thinner than the 7-8 nm usually adopted. However, the oxide thickness has barely scaled over the many Flash technology generations, remaining far away from its theoretical limit, because it was soon realized [70,166,167] that repeated P/E cycles led to degradation of the tunnel oxide characteristics, enhanced leakage and worse retention. The enhanced oxide leakage at low fields after electrical stress is known as stress-induced leakage current, or SILC [168,169].…”

Section: Retention After Cycling and Silcmentioning

confidence: 99%

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Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

2017

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Abstract:We review the state-of-the-art in the understanding of planar NAND Flash memory reliability and discuss how the recent move to three-dimensional (3D) devices has affected this field. Particular emphasis is placed on mechanisms developing along the lifetime of the memory array, as opposed to time-zero or technological issues, and the viewpoint is focused on the understanding of the root causes. The impressive amount of published work demonstrates that Flash reliability is a complex yet well-understood field, where nonetheless tighter and tighter constraints are set by device scaling. Three-dimensional NAND have offset the traditional scaling scenario, leading to an improvement in performance and reliability while raising new issues to be dealt with, determined by the newer and more complex cell and array architectures as well as operation modes. A thorough understanding of the complex phenomena involved in the operation and reliability of NAND cells remains vital for the development of future technology nodes.

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Section: Endurancementioning

confidence: 55%

Section: Retention After Cycling and Silcmentioning

confidence: 99%

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

2017

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“…The floating gate was patterned to achieve a gate coupling coefficient of 0.86, where the gate coupling coefficient is defined as interpoly dielectric capacitance divided by total capacitance.8 After the formation of the 140 A interpoly oxide, 1500 A of amorphous silicon was deposited for the control gate layer and doped by phosphorous ion implantation. The floating gate stack was patterned by reactive ion etch (RIE), and symmetric junctions were formed by ion implantation of 5 )< 1014 cm2 phosphorus at 10 key and annealed for 15 contact metal were deposited, and the devices were annealed in forming gas. The interpoly oxide was formed either by a high temperature furnace oxidation or by low thermal budget RTCVD.…”

Section: Methodsmentioning

confidence: 99%

Impact of Floating Gate Dopant Concentration and Interpoly Dielectric Processing on Tunnel Dielectric Reliability

Heinisch

Hornung

Linkous

et al. 1998

J. Electrochem. Soc.

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The influence of gate dopant concentration and thermal budget on the reliability of tunnel dielectric films was studied. Metal oxide semiconductor (MOS) capacitors were furnace annealed after gate formation, floating gate devices were fabricated with interpoly dielectric films either grown by furnace oxidation or deposited by rapid thermal chemical vapor deposition (RTCVD); the latter process is associated with a much lower thermal budget. Ion implanted amorphous silicon was employed for the gate electrodes of the MOS capacitors and for the floating gate layers of the memory devices. The reliability of the dielectrics was evaluated under a constant current stress, and the cycling endurance of the floating gate devices was examined. It was found that tap generation and charge trapping increase with increasing annealing time and increasing dopant concentration, while charge to breakdown (Q84) decreases with increasing annealing time. The cycling endurance plot for the floating gate devices revealed little distortion of the threshold voltage window for devices with the low thermal budget RTCVD interpoly dielectric film. Based on this study, a low thermal budget process is preferable for the formation of the interpoly dielectric.

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“…This explains why the oxide layer on the tip reduces the emission current by approximately three orders of magnitude. When emitted, some electrons may be trapped in the potential well of the oxide vacuum interface, and some in the bulk oxide electron traps [7,9,18]. These trapped electrons reduce the oxide field and can be another cause of the initial decrease of the emission current.…”

Section: Emission Stabilitymentioning

confidence: 99%

A study of emitter formation by various etching techniques and its application to flat panel display

Lee

Huang

1995

Journal of the Chinese Institute of Engineers

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In view of the potential advantages of using field-emission cathodes as electron sources, a renewed interest in advanced IC technology utilizing silicon-based coldcathode microelectronics is emerging. However, some etching results concerning emitter formation are still unknown. This paper presents a study of emitter formation by various wet and dry etching methods. Some geometrical models are given for the analysis of anisotropic etching results. The emission features from different emitter arrays are also given for comparison. Through understanding the emission characteristics of various emitter arrays, a novel design for Field-Emission Flat Panel Display is proposed.

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Reliability Aspects of a Floating Gate E2 PROM

Cited by 22 publications

References 0 publications

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

Impact of Floating Gate Dopant Concentration and Interpoly Dielectric Processing on Tunnel Dielectric Reliability

A study of emitter formation by various etching techniques and its application to flat panel display

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