Reliability characterization and activity analysis of lowRISC internal modules against single event upsets using fault injection and RTL simulation

Mohseni, Zeynab; Reviriego, Pedro

doi:10.1016/j.micpro.2019.102871

Cited by 5 publications

(4 citation statements)

References 7 publications

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“…Regarding RISC-V, since the RISC-V itself is an open-source hardware, many RoT modifications have been proposed directly into the hardware system. Many RISC-V RoT examples are the Rambus CryptoManager [28] and the OpenTitan [29]. The RoT is the designated location for keeping and overseeing the root key and certificates of the device.…”

Section: Introductionmentioning

confidence: 99%

A Trusted Execution Environment RISC-V System-on-Chip Compatible with Transport Layer Security 1.3

Kieu-Do-Nguyen,

Nguyen,

Dang

et al. 2024

Electronics

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The Trusted Execution Environment (TEE) is designed to establish a safe environment that prevents the execution of unauthenticated programs. The nature of TEE is a continuous verification process with hashing, signing, and verifying. Such a process is called the Chain-of-Trust, derived from the Root-of-Trust (RoT). Typically, the RoT is pre-programmed, hard-coded, or embedded in hardware, which is locally produced and checked before booting. The TEE employs various cryptographic processes throughout the boot process to verify the authenticity of the bootloader. It also validates other sensitive data and applications, such as software connected to the operating system. TEE is a self-contained environment and should not serve as the RoT or handle secure boot operations. Therefore, the issue of implementing hardware for RoT has become a challenge that requires further investigation and advancement. The main objective of this proposal is to introduce a secured RISC-V-based System-on-Chip (SoC) architecture capable of securely booting a TEE using a versatile boot program while maintaining complete isolation from the TEE processors. The suggested design has many cryptographic accelerators essential for the secure boot procedure. Furthermore, a separate 32-bit MicroController Unit (MCU) is concealed from the TEE side. This MCU manages sensitive information, such as the root key, and critical operations like the Zero Stage BootLoader (ZSBL) and key generation program. Once the RoT is integrated into the isolated sub-system, it becomes completely unavailable from the TEE side, even after booting, using any method. Besides providing a secured boot flow, the system is integrated with essential crypto-cores supporting Transport Layer Security (TLS) 1.3. The chip is finally fabricated using the Complementary Metal–Oxide–Semiconductor (CMOS) 180 nm process.

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Section: Introductionmentioning

confidence: 99%

A Trusted Execution Environment RISC-V System-on-Chip Compatible with Transport Layer Security 1.3

Kieu-Do-Nguyen,

Nguyen,

Dang

et al. 2024

Electronics

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“…In consequence, logical fault injection has therefore gained attention, as it yields early reliability assessment, even during the design phases, at lower costs. It includes 2 main strategies: emulation-based fault injection, in which the real system is either emulated, usually with an FPGA, or the faults are emulated on real devices [8]; and simulation-based fault injection, where a model of the system to be tested is used, and faults are produced during its simulation [9,10]. These tools offer different levels of accuracy (bit accurate, cycle accurate) and observability depending on the processor model that is employed: ISA (Instruction Set Architecture) model, RTL (Register Transfer Level) model, etc.…”

Section: Introductionmentioning

confidence: 99%

Evaluation of fault injection tools for reliability estimation of microprocessor-based embedded systems

Aponte-Moreno

Isaza-Gonzalez²,

Serrano-Cases³

et al. 2023

Microprocessors and Microsystems

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“…With scaling down of the feature size of chips, field programmable gate arrays (FPGAs) and ASIC are more susceptible to the effects of ionizing irradiation, especially SEUs, which seriously threaten the reliability of circuits [1,2,3]. To reduce impacts of SEUs, triple modular redundancy (TMR), a highly efficient mitigation technique, is the most used method [4,5,6]. Metastability caused by CDC is an another problem which threaten the reliability of circuits.…”

Section: Introductionmentioning

confidence: 99%

“…Therefore, the specific modifications for synchronizers and their corresponding transmission protocols in TMR applications are required. At present, majority of researches focus on antiirradiation design [11,12,13,14,15,16,17], irradiation test [18,19,20,21,22], CDC design [7,23,24], metastable parameter test [25,26,27]. However, they have not addressed the problem combining both effects of SEUs and metastability.…”

Section: Introductionmentioning

confidence: 99%

Design and verification for CDC synchronization based on TMR

Fan

Deng

2020

IEICE Electron. Express

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Triple modular redundancy (TMR) is widely used in FPGA/ASIC circuits to protect circuits against single event upsets (SEUs). However, because of the interference of metastability on signal transmission across clock domains, the TMR circuits' capability against SEUs is reduced greatly. In order to solve this problem, a cross-clock transmission solution which could be applied in TMR circuits are presented. In addition, simulationbased verification which combined protocol assertions, metastable injection and forced inversion is proposed to succeed in verifying the availability of the solution based on TMR circuits.

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Reliability characterization and activity analysis of lowRISC internal modules against single event upsets using fault injection and RTL simulation

Cited by 5 publications

References 7 publications

A Trusted Execution Environment RISC-V System-on-Chip Compatible with Transport Layer Security 1.3

A Trusted Execution Environment RISC-V System-on-Chip Compatible with Transport Layer Security 1.3

Evaluation of fault injection tools for reliability estimation of microprocessor-based embedded systems

Design and verification for CDC synchronization based on TMR

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