2013 IEEE 63rd Electronic Components and Technology Conference 2013
DOI: 10.1109/ectc.2013.6575547
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Reliability evaluation of a CoWoS-enabled 3D IC package

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Cited by 55 publications
(5 citation statements)
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“…Because of the drive of AI, ML, and 5 G, the semiconductors such as the sliced field-programmable gate arrays density and I/Os increase and pad-pitch decreases. Even a 12 build-up layers (6-2-6), organic package substrate is not enough to support the sliced chips and a TSV-interposer is needed [121][122][123][124][125][126][127][128][129][130][131][132][133][134][135][136][137][138][139]. TSMC called this kind of structure CoWoS (chip-on-wafer-on substrate) [137,138].…”
Section: Opportunities For Fan-out Wafer-level Packagingmentioning
confidence: 99%
“…Because of the drive of AI, ML, and 5 G, the semiconductors such as the sliced field-programmable gate arrays density and I/Os increase and pad-pitch decreases. Even a 12 build-up layers (6-2-6), organic package substrate is not enough to support the sliced chips and a TSV-interposer is needed [121][122][123][124][125][126][127][128][129][130][131][132][133][134][135][136][137][138][139]. TSMC called this kind of structure CoWoS (chip-on-wafer-on substrate) [137,138].…”
Section: Opportunities For Fan-out Wafer-level Packagingmentioning
confidence: 99%
“…[25]. Most recent advances in packaging technologies, which make HI-based SoIC superchips possible, include ultra-fine pitch interconnect fabrics and chip-on-wafer-on-substrate (CoWoS) packaging that smartly leverage matured and advanced IC fabrication technologies of IC-scale critical dimensions (down to a few µm and moving into the nm domain) that support hetero-integrating chiplets/dielets onto IC substrates to achieve wafer-level chip-scale heterogeneous integration of microsystems [26][27][28]. One of the most successful SoIC examples is the new Nvidia Blackwell GB200 superchip (integrating 208B transistors in a 4 nm CMOS) that stitches two B200 GPU cores (four dies), one Grace CPU die, and NVSwitch high-bandwidth interface dies (10 Tb/s) together in CoWoS packaging to deliver a record 20 petaflops in AI computing [28].…”
Section: Introductionmentioning
confidence: 99%
“…Reliability is a major barrier to realizing HI-enabled SoICs in terms of both performance and costs [27,[29][30][31]. In particular, ESD is the most important reliability problem for heterogeneous integration technologies and ESD protection design becomes extremely challenging for realizing SoIC superchips [29,32,33].…”
Section: Introductionmentioning
confidence: 99%
“…3 shows the Virtex-7 HT family shipped by Xilinx in 2013. In 2011, Xilinx asked TSMC to fabricate its field programable gate array (FPGA) SoC with 28 nm process technology [4,5]. Because of the large chip size, the yield was very poor.…”
Section: Introductionmentioning
confidence: 99%