Reliability in MOS integrated circuits

Woods, M. H.; Euzent, B.L.

doi:10.1109/iedm.1984.190639

“…Better understanding and trade-off studies are necessary; then optimization in LDD design and process can be achieved. Hot-electron-induced deg radation and other reliability concerns such as thin oxide quality and electromigration may place funda mental limits in scaling CMOS devices to the submicron regime [62]. In CMOS isolation, both parasitic FETs and bipolars must be considered in order to prevent field inversion, punch through, and latch-up.…”

Section: Summary and Future Trendsmentioning

confidence: 99%

CMOS — The emerging VLSI technology

Chen

¹

1986

IEEE Circuits Devices Mag.

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This paper reviews the recent evolution in CMOS as the emerging very-large-scale-integrated (VLSI) technology. Various CMOS tech nologies and their impact on circuit performance and reliability are dis cussed and compared in generic and special circuit applications. Key issues in CMOS scaling, such as hot-electron effects, buried-channel character istics, latch-up, and isolation requirements, are briefly described. State-ofthe-art CMOS design rules are also addressed. The paper concludes with a discussion on the future trends of CMOS technology development in VLSI circuits.

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“…Extensive research in the field of neuromorphic engineering in recent years has led to the development of various bioinspired circuits on silicon chips using advanced CMOS technology nodes [6]- [13]. Therefore, it is notable to consider reliability issues such as Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI) [14]- [17] at these advanced nodes. BTI leads to the shift of device parameters like the threshold voltage (ΔVTH), drain current (ID), subthreshold slope (ΔS), transconductance (gm) because of gradual accumulation of charges at or near gate insulator [18]- [24].…”

Section: Introductionmentioning

confidence: 99%

Reliability-Aware Design of Spike-Event Neuromorphic Circuits

Shaik¹,

Picardo²,

Singhal³

et al. 2021

Preprint

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Very Large Scale Integration (VLSI) based neuromorphic circuits also known as Silicon Neurons (SiNs) emulate the electrophysiological behavior of biological neurons. With the advancement in technology, neuromorphic systems also lead to various reliability issues and hence making their study important. Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI) are the two major reliability issues present in VLSI circuits. In this work, we have investigated the combined effect of BTI and HCI on the two types of integrate-and-fire based SiNs namely (a) Axon-Hillock and (b) Simplified Leaky integrate-and-fire circuits using their key performance parameters. Novel reliability-aware AH and SLIF circuits are proposed to mitigate the reliability issues. Proposed reliability-aware designs show negligible deviation in performance parameters after aging. The time-zero process variability analysis is also carried out for proposed reliability-aware SiNs. The power consumption of existing and proposed reliability-aware neuron circuits is analyzed and compared.<br>

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“…Extensive research in the field of neuromorphic engineering in recent years has led to the development of various bioinspired circuits on silicon chips using advanced CMOS technology nodes [6]- [13]. Therefore, it is notable to consider reliability issues such as Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI) [14]- [17] at these advanced nodes. BTI leads to the shift of device parameters like the threshold voltage (ΔVTH), drain current (ID), subthreshold slope (ΔS), transconductance (gm) because of gradual accumulation of charges at or near gate insulator [18]- [24].…”

Section: Introductionmentioning

confidence: 99%

Reliability-Aware Design of Spike-Event Neuromorphic Circuits

Shaik¹,

Picardo²,

Singhal³

et al. 2021

Preprint

View full text Add to dashboard Cite

Very Large Scale Integration (VLSI) based neuromorphic circuits also known as Silicon Neurons (SiNs) emulate the electrophysiological behavior of biological neurons. With the advancement in technology, neuromorphic systems also lead to various reliability issues and hence making their study important. Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI) are the two major reliability issues present in VLSI circuits. In this work, we have investigated the combined effect of BTI and HCI on the two types of integrate-and-fire based SiNs namely (a) Axon-Hillock and (b) Simplified Leaky integrate-and-fire circuits using their key performance parameters. Novel reliability-aware AH and SLIF circuits are proposed to mitigate the reliability issues. Proposed reliability-aware designs show negligible deviation in performance parameters after aging. The time-zero process variability analysis is also carried out for proposed reliability-aware SiNs. The power consumption of existing and proposed reliability-aware neuron circuits is analyzed and compared.<br>

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Reliability in MOS integrated circuits

Cited by 17 publications

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CMOS — The emerging VLSI technology

CMOS — The emerging VLSI technology

Reliability-Aware Design of Spike-Event Neuromorphic Circuits

Reliability-Aware Design of Spike-Event Neuromorphic Circuits

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