Reliability models of data retention and read-disturb in 2-bit nitride storage flash memory cells

Wang, T.; Tsai, Wen-Jer; Gu, S.H.; Chan, Chuan-Tsung; Yeh, Chih-Ting; Zous, N.K.; Lu, Tsung-Chien; Pan, S.C.; Lu, Chih‐Yuan

doi:10.1109/iedm.2003.1269202

Cited by 36 publications

(18 citation statements)

References 9 publications

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“…Our results may not be compared to studies of NROM devices subjected to negative gate stress in which vertical charge loss was reported [24].…”

Section: E Lateral Versus Vertical Charge Transportmentioning

confidence: 62%

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Data retention reliability model of NROM nonvolatile memory products

Janai¹,

Eitan²,

Shappir³

et al. 2004

IEEE Trans. Device Mater. Relib.

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Post cycling data retention reliability model of NROM devices is presented. The degradation rate of the threshold voltage of cycled cells is shown to be a multiplication of three functions: 1) bit density; 2) endurance; and 3) storage time and temperature. The functions are fitted to experimental results of products of three technology nodes. The retention loss is interpreted in terms of thermally activated lateral migration of trapped holes in the ONO layer. The holes' migration quenches the electrons' field over the channel of the device, degrading its threshold voltage. The migration process is presented as a dispersive transport process. Saturation of the retention loss is demonstrated at threshold voltage levels well above the neutral state of the device. From the retention loss function we derive a time-to-failure formula and an expression for the thermal acceleration factor of NROM products useful for determining stress conditions for accelerated reliability tests.

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“…Our results may not be compared to studies of NROM devices subjected to negative gate stress in which vertical charge loss was reported [24].…”

Section: E Lateral Versus Vertical Charge Transportmentioning

confidence: 62%

“…According to the vertical charge loss model the rate of charge loss is controlled by PF emission of electrons from nitride traps. The emitted electrons leak by trap-assisted tunneling (TAT) through the bottom oxide [23], [24].…”

Section: E Lateral Versus Vertical Charge Transportmentioning

confidence: 99%

Data retention reliability model of NROM nonvolatile memory products

Janai¹,

Eitan²,

Shappir³

et al. 2004

IEEE Trans. Device Mater. Relib.

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“…2. The charge detrapping current in the SONOS cell follows a linear dependence on temperature, which is expected from the FP emission model, i.e., I g ∝ kT/t [8]. The gate leakage current in the HfO 2 cell, however, 0741-3106/$25.00 © 2008 IEEE apparently deviates from a linear relationship.…”

Section: Measurement Resultsmentioning

confidence: 94%

“…Second, the gate current in both SONOS [6] and HfO 2 dot flash cells exhibits 1/t time dependence. The 1/t characteristic can be derived either from a tunneling front model [7] or from a Frenkel-Poole (FP) emission model [8]. To distinguish these two models, we compare temperature dependence of the gate current in the two cells in Fig.…”

Section: Measurement Resultsmentioning

confidence: 99%

Charge Retention Loss in a $\hbox{HfO}_{2}$ Dot Flash Memory via Thermally Assisted Tunneling

Wang

et al. 2008

IEEE Electron Device Lett.

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The charge loss mechanism in a hafnium oxide (HfO 2 ) dielectric dot flash memory is investigated. We measure the temperature and time dependence of a charge loss induced gate leakage current in a large area cell directly. We find that 1) the charge loss is through a top oxide in the cell and 2) the stored charge emission process exhibits an Arrhenius relationship with temperature, as opposed to linear temperature dependence in a semiconductor-oxide-nitride-oxide-semiconductor flash memory. A thermally activated tunneling front model is proposed to account for the charge loss behavior in a HfO 2 dot flash memory.Index Terms-Charge retention loss, hafnium oxide (HfO 2 ) dot flash, thermally activated tunneling.

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“…At the beginning of the relaxation process there is a limited decrease of V t (~50-200 mV) even for the one-time programmed cell. Additional "fast" memory window loss (~250-500mV) is observed after 1k-100k program-erase cycles [5][6][7].…”

Section: Introductionmentioning

confidence: 99%

Computer and experimental study of the gate dielectric in a memory transistor

Avichail-Bibi¹,

Fuks²,

Kiv³

et al. 2007

WIT Transactions on Modelling and Simulation, Vol 46

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We demonstrate a novel approach that enables combining microscopic studies of the behaviour of the injected charge (IC) in the gate dielectric (GD) of the memory transistor and the description of kinetics of memory device service parameters. To study the microscopic processes of the redistribution of the IC in the GD a special package of programs was developed that allows the modelling the migration of injected electrons and holes in the GD. The model accounts real properties of dielectric (spatial distribution of local centres and their characteristics, the dielectric constant and its changes on the microscopic distances, a complex composition of dielectric, temperature conditions and the geometry of the GD). The results of the computer simulation of microscopic characteristics of the IC were used as input data for the commercial Device simulation program "Medici". We found a correlation between microscopic characteristics of IC in GD and the service parameters of the memory device and realized the feedback procedure changing the GD characteristics in the simulation model.

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Reliability models of data retention and read-disturb in 2-bit nitride storage flash memory cells

Cited by 36 publications

References 9 publications

Data retention reliability model of NROM nonvolatile memory products

Data retention reliability model of NROM nonvolatile memory products

Charge Retention Loss in a $\hbox{HfO}_{2}$ Dot Flash Memory via Thermally Assisted Tunneling

Computer and experimental study of the gate dielectric in a memory transistor

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