Reliability-Oriented Placement and Routing Algorithm for SRAM-Based FPGAs

Huang, Keheng; Hu, Yu; Li, Xiaowei

doi:10.1109/tvlsi.2013.2239318

Cited by 19 publications

(4 citation statements)

References 24 publications

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“…However, when a FPGA netlist touches upon sequential logic circuits, they cannot work. To address this issue, a cube based analysis algorithm was proposed in [13] to estimate the fault propagation probability of the FPGA netlist. In [14], a software error propagation analysis technique is proposed to evaluate the soft error rate of FPGA.…”

Section: Literature Reivewsmentioning

confidence: 99%

A Fault Propagation Model for FPGA Netlist with Un-Reconvergence Paths

Wang¹,

Chen²,

Lu³

2018

2018 5th International Conference on Information Science and Control Engineering (ICISCE)

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In this paper, we propose an analysis method of fault propagation based on the FPGA netlist with unreconvergence path. First of all, we analyze the characteristics of common components in the netlist, calculate the fault propagation probability of these components, and then establish a netlist-level fault propagation model based on the interconnection topological structure of the components in the netlist. When a fault happens at input ports of the netlist, we analyze the fault propagation characteristics in the whole netlist, calculate the probability of the fault propagating from input to output ports, and find out the input port which is most likely to cause the fault. Finally, we verify the model presented in this paper by experiments. The experimental results show that the estimated error of fault propagation probability is negligible. It is less than 0.1% compared to the corresponding testing results.

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Section: Literature Reivewsmentioning

confidence: 99%

A Fault Propagation Model for FPGA Netlist with Un-Reconvergence Paths

Wang¹,

Chen²,

Lu³

2018

2018 5th International Conference on Information Science and Control Engineering (ICISCE)

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“…For example, an interesting technique has been presented in [14] which manages the signals between functions in such a way that multiple errors affecting two different connections are not possible. In a similar approach, [15] studies both fault occurrence and error propagation probabilities to propose a reliability-oriented placement and routing algorithm. Anyway, all these techniques can be applied to a given hardware task and, as indicated by [16], they can be used in combination with other design-based methods to increase the reliability of the circuits.…”

Section: Related Workmentioning

confidence: 99%

Reliability Improvement of Hardware Task Graphs via Configuration Early Fetch

Ramezani

Sedaghat

Clemente

2017

IEEE Trans. VLSI Syst.

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Abstract-This study presents a technique to improve the reliability and the Mean Time to Failure (MTTF) of hardware task graphs running on reconfigurable computers. This technique, which has been named Task Early-fetch, can be applied to a sequence of one or several applications, represented as task graphs. It consists in carrying out the reconfiguration of some tasks within the execution of the previous task graph, plus increasing the redundancy level of the early-fetched tasks. Experimental results on actual task graphs show the positive impacts of the proposed technique. Thus, without deteriorating the execution time (makespan), on average, a 114% MTTF improvement is achieved for no-fault-tolerant task graphs, and the improvement is more significant when applying to faulttolerant task graphs. Finally, this paper presents a hardware implementation of a manager that applies these techniques at run-time and steers the execution of the running task graphs. It demonstrates that, with 0.03% consumption of FFs and LUTs and also 1.22% occupancy of BRAMs available on a Xilinx Virtex UltraScale XCVU095-2FFVA2104E FPGA, the required run-time computations can be carried out in negligible delays.

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“…Furthermore, static analysis can not be used for sequential circuits. Based on the method of static analysis, the paper [14] proposed a cube-based analysis algorithm to estimate the EPPs of sequential circuits. However, using self-multiplication of the probability matrix to calculate the EPPs for multiple clock cycles is not appropriate, because it will lead to contradiction that a probability is beyond the theoretical upper bound [14].…”

Section: Introductionmentioning

confidence: 99%

Soft Error Susceptibility Analysis for Sequential Circuit Elements Based on EPPM

Cai¹,

Kuang²,

Liu³

et al. 2015

JSTS:Journal of Semiconductor Technology and Science

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Abstract-Due to the reduction in device feature size, transient faults (soft errors) in logic circuits induced by radiations increase dramatically. Many researches have been done in modeling and analyzing the susceptibility of sequential circuit elements caused by soft errors. However, to the best knowledge of the authors, there is no work which has well considerated the feedback characteristics and the multiple clock cycles of sequential circuits. In this paper, we present a new method for evaluating the susceptibility of sequential circuit elements to soft errors. The proposed method uses four Error Propagation Probability Matrixs (EPPMs) to represent the error propagation probability of logic gates and flip-flops in current clock cycle. Based on the predefined matrix union operations, the susceptibility of circuit elements in multiple clock cycles can be evaluated. Experimental results on ISCAS'89 benchmark circuits show that our method is more accurate and efficient than previous methods.

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Reliability-Oriented Placement and Routing Algorithm for SRAM-Based FPGAs

Cited by 19 publications

References 24 publications

A Fault Propagation Model for FPGA Netlist with Un-Reconvergence Paths

A Fault Propagation Model for FPGA Netlist with Un-Reconvergence Paths

Reliability Improvement of Hardware Task Graphs via Configuration Early Fetch

Soft Error Susceptibility Analysis for Sequential Circuit Elements Based on EPPM

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