Reliability properties of low voltage PZT ferroelectric capacitors and arrays

A Thin Film Approach to Engineering Functionality into Oxides

“…Orientation control is vital to the preparation of samples suitable for establishing the intrinsic properties of materials, especially those that cannot be prepared as bulk single crystals due to their metastability, high melting temperatures, or phase transitions that occur on cooling. When it comes to applications, techniques that can improve the functional properties of oxide films by controlling film texture through epitaxial growth on a grain‐by‐grain basis (local epitaxy) are also utilized, e.g., ion‐beam‐assisted deposition 254,255 and rolling‐assisted biaxially textured substrates 256,257 for the growth of YBa 2 Cu 3 O 7 superconducting cables 258 as well as Pb(Zr,Ti)O 3 in FeRAMs 259 …”

“…For functional oxides with perovskite structures (e.g., SrTiO 3 , BiMnO 3 , BiFeO 3 , Pb(Zr,Ti)O 3 , and PbZn 1/3 Nb 2/3 O 3 –PbTiO 3 ), chemically and structurally compatible perovskite substrate materials are needed. Intensive work on high‐temperature superconductors stimulated the production of many perovskite single crystals 230–269 to diameters up to 4 in. as well as spawning a number of new perovskite and perovskite‐related substrates 270–273 .…”

Manufacturable High-Density 8 Mbit One Transistor–One Capacitor Embedded Ferroelectric Random Access Memory

“…Data retention was evaluated using a slight modification of the standard ''same state'' and ''opposite state'' retention test methodology. 20,21) Briefly, the procedure involves the following: bits are written in either the Data 0 or Data 1 state, baked at 125 C, then read by applying a unipolar pulse to obtain the same state retention; the bits are then written to a state opposite to the initially written state, baked at 85 C, delayed for >1 s, and read to obtain the opposite state retention. Wafers with data separation margins greater than the set value for screen have shown no bit fails for retention bakes up to 1000 h, suggesting a lifetime of more than 10 years at 85 C. Figure 6 is a Reference Voltage Shmoo plot of wafers at time zero and 1000 h retention bake.…”

Bit Distribution and Reliability of High Density 1.5 V Ferroelectric Random Access Memory Embedded with 130 nm, 5 lm Copper Complementary Metal Oxide Semiconductor Logic

“…Between the two types of retention characteristics, samestate (SS) retention and opposite state (OS) retention, it is the latter that is worse; 16) we, therefore, focus on the OS retention characteristics for packaged arrays. While an extensive description of the measurement protocols are available elsewhere, 16,17) briefly, the procedure involves the following: bits are written in either the Data 0 or Data 1 state, baked at 150 C, then read by applying a unipolar pulse to obtain the same state retention; the bits are then written to a state opposite to the initially written state, delayed for >1 s, and read to obtain the opposite state retention. The OS retention is, thus, an indicator of the charge stability of the oppositely written state following a long (designated) retention period in the originally written state at the highest operating device temperature.…”

“…The difference in behavior between opposite state D0 and opposite state D1 has been noted in our previous works. 16,17) The Data 0 magnitude is the difference between the linear term measured during the rising edge and falling edge of the sense pulse. Therefore, a shift in the hysteresis loop will increase the linear term, but the net difference (risingfalling) does not change very dramatically with high temperature storage.…”